Semiconductor device, method for manufacturing the same, circuit substrate, electro-optical apparatus, and electronic equipment

• US 7,098,127 B2
• Filed: 12/02/2003
• Issued: 08/29/2006
• Est. Priority Date: 12/02/2002
• Status: Active Grant

• Current Assignee: Seiko Epson Corporation (Seiko Group)
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Ito, Haruki
• Primary Examiner(s): PHAM, THANHHA S
• Application Number:
  US10/726,275
• Publication Number:
  US 20040145031A1
• Time in Patent Office: 1,001 Days
• Field of Search: 438/612, 438/613, 438/614, 438622-625, 438/674, 438/678, 438687-688
• US Class Current: 438/614
• CPC Class Codes: G02F 1/13458 Terminal pads
• CPC Class Codes: H01L 21/4846 Leads on or in insulating or insulated substrates, e.g. metallisation H01L21/4821 takes precedence; metallisation of ceramics in general C04B41/51; printed circuits H05K3/00
• CPC Class Codes: H01L 2224/0236 Shape of the insulating layers therebetween
• CPC Class Codes: H01L 2224/02375 Top view
• CPC Class Codes: H01L 2224/02377 Fan-in arrangement
• CPC Class Codes: H01L 2224/024 Material of the insulating layers therebetween
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05099 Material
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/114 by blanket deposition of the material of the bump connector
• CPC Class Codes: H01L 2224/1145 Physical vapour deposition [PVD], e.g. evaporation, or sputtering
• CPC Class Codes: H01L 2224/1146 Plating
• CPC Class Codes: H01L 2224/1161 Physical or chemical etching
• CPC Class Codes: H01L 2224/11622 Photolithography
• CPC Class Codes: H01L 2224/11901 with repetition of the same manufacturing step
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/13008 Bump connector integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13013 being rectangular or square
• CPC Class Codes: H01L 2224/13018 comprising protrusions or indentations
• CPC Class Codes: H01L 2224/13099 : Material
• CPC Class Codes: H01L 2224/1319 : with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/13582 : Two-layer coating
• CPC Class Codes: H01L 2224/13599 : Material
• CPC Class Codes: H01L 2224/13644 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13666 : Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/29099 : Material
• CPC Class Codes: H01L 2224/29599 : Material
• CPC Class Codes: H01L 23/485 : consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 24/02 : Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/14 : of a plurality of bump connectors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00013 : Fully indexed content
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0103 : Zinc [Zn]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

A semiconductor device is provided with a plurality of protrusions which are made of a resin and which protrude higher than electrodes, and conductive layers which are electrically connected to the electrodes and which cover the top surfaces of the protrusions. A method for manufacturing the semiconductor device includes a step of applying a layer of the resin to the semiconductor device except for the electrodes, a step of patterning the conductive layers on the electrodes and the layer of the resin in accordance with the protrusions, and a step of removing the layer of the resin located between the conductive layers by the use of the patterned conductive layers as masks so as to form the protrusions.

Claims

1. A method for manufacturing a semiconductor comprising:

forming a plurality of electrodes on portions of a semiconductor element

forming a first conductive layer by electroless nickel plating on the plurality of the electrodes before applying a layer of a resin in a subsequent step;

applying the layer of the resin to the semiconductor element in a region of the semiconductor element that does not include the electrodes, the layer of the resin being applied such that a height of the layer of the resin is greater than a height of the electrodes;

forming a second conductive layer over the plurality of the electrodes and the layer of the resin, the second conductive layer being connected to the first conductive layer and covering a top surface of the layer of the resin;

patterning the second conductive layer on the electrodes and the layer of the resin in a predetermined pattern; and

removing portions of the layer of the resin using the patterned second conductive layer as a mask so that remaining portions of the layer of the resin form a plurality of protrusions.

2. The method for manufacturing a semiconductor device according to claim 1, wherein the layer of the resin is removed by plasma processing.

3. The method for manufacturing a semiconductor device according to claim 1, wherein the second conductive layer is formed by sputtering.

4. The method for manufacturing a semiconductor device according to claim 1, wherein the second conductive layer is formed by plating.