Local bit select circuit with slow read recovery scheme

• US 7,102,946 B2
• Filed: 02/09/2005
• Issued: 09/05/2006
• Est. Priority Date: 02/09/2005
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Pelella, Antonio R.
• Primary Examiner(s): MAI, SON LUU
• Application Number:
  US11/054,148
• Publication Number:
  US 20060176728A1
• Time in Patent Office: 573 Days
• Field of Search: None
• US Class Current: 365/205
• CPC Class Codes: G11C 11/41 forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
• CPC Class Codes: G11C 11/413 Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 2207/065 Sense amplifier drivers
• CPC Class Codes: G11C 7/06 Sense amplifiers; Associated circuits , e.g. timing or triggering circuits
• CPC Class Codes: G11C 7/08 Control thereof

Abstract

Local bit line pairs in a domino SRAM include an amplifier to amplify the voltage differential across the bit lines during a read operation if a cell in the local group of cells has been identified as a slow to read cell. The amplifier includes a transistor switch that is turned on by a timing pulse during the read operation, but only if the Array Built In Self-Test (ABIST) has detected a slow to read cell in the local group. If there is no slow cell, the amplifier is not activated, and the domino read operation is carried out. The amplifier can be used globally across the SRAM or selectively in certain sub-arrays.

Claims

1. A domino SRAM comprising in combination:

a local bit line amplifier connected across a local bit line pair;

a transistor switch coupled to said amplifier, said switch in one state rendering said amplifier operative to amplify a voltage difference between said local bit line pair and in another state rendering said amplifier dormant;

means to place said switch in said one state during a read operation if a cell serviced by said local bit line pair has been determined to be a slow to read cell.

3. A domino SRAM as in claim 1 wherein said local bit line amplifier includes a pair of field effect transistors cross-coupled between said local bit line pair.

4. A domino SRAM as in claim 3 wherein said transistor switch is a field effect transistor.

5. A domino SRAM as in claim 4 wherein said pair of field effect transistors and said transistor switch are N-type field effect transistors.

6. A domino SRAM as in claim 1 wherein said means includes a latch responsive to an array built in self-test generated signal.

7. A domino SRAM as in claim 3 wherein said means includes a latch responsive to an array built in self-test generated signal.

8. A domino SRAM as in claim 4 wherein said means includes a latch responsive to an array built in self-test generated signal.

2. A method for operating a domino SRAM including the steps of:

detecting a slow to read cell in an SRAM array serviced by a local bit line pair;

amplifying the voltage between said local bit line pair during a read operation in response to said detecting step.

9. A method as in claim 2 wherein said amplifying step is carried out only in response to said detecting step.

10. A method as in claim 2 wherein said detecting step includes the step of a built in self-test of said SRAM.

11. A method as in claim 9 wherein said detecting step includes the step of a built in self-test of said SRAM.

12. A method as in claim 10 wherein including the step of setting a latch when said built in self-test detects a slow to read cell.

13. A method as in claim 11 including the step of setting a latch when said built in self-test detects a slow to read cell.

14. A domino SRAM system comprising in combination:

means to amplify a voltage difference across a local bit line pair;

means to detect a slow to read cell in an SRAM array serviced by said local bit line pair;

means to enable said means to amplify in response to detection of a slow to read cell.

15. A domino SRAM system as in claim 14 further including means to disable said means to amplify.

16. A domino SRAM system as in claim 14 wherein said means to detect includes built in self-test means.

17. A domino SRAM system as in claim 15 wherein said means to detect includes built in self-test means.

18. A domino SRAM system as in claim 15 wherein said means to enable and said means to disable includes a latch.

19. A domino SRAM system as in claim 15 wherein said means to enable and said means to disable includes a latch set by said built in self-test means.

20. A domino SRAM system as in claim 17 wherein said means to enable and said means to disable includes a latch set by said built in self-test means.