Planar pedestal multi gate device

• US 7,105,391 B2
• Filed: 03/04/2004
• Issued: 09/12/2006
• Est. Priority Date: 03/04/2004
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Doris, Bruce B., Zhang, Ying, Petrus, John Charles
• Primary Examiner(s): Nguyen, Tuan H.
• Application Number:
  US10/708,451
• Publication Number:
  US 20050196912A1
• Time in Patent Office: 922 Days
• Field of Search: 438/149, 438/151, 438/197, 438/299
• US Class Current: 438/151
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body

Abstract

A method of forming a transistor comprises disposing a planar platform (or pedestal, or layer) of silicon atop a support structure of oxide which is atop a substrate; forming gate structures both atop and beneath the planar platform; and forming source and drain diffusions within the planar platform. The gate structures which are formed beneath the planar platform may smaller than the planar platform, and may be aligned with the gate structures which are formed atop the planar platform. A transistor formed by the method is also disclosed.

Claims

1. Method of forming a transistor comprising:

disposing a planar platform of silicon atop a support structure of oxide which is atop a substrate;

wherein the support structure is disposed beneath the planar platform;

forming multiple gate structures both atop and beneath the planar platform; and

forming source and drain diffusions within the planar platform.

2. Method, according to claim 1, wherein:

the gate structures which are formed beneath the planar platform are smaller than the planar platform.

3. Method, according to claim 1, wherein:

the gate structures which are formed beneath the planar platform are aligned with the gate structures which are formed atop the planar platform.

4. Method, according to claim 1, wherein:

the platform of silicon is supported from below by the support structure.

5. Method, according to claim 1, wherein:

the support structure is centered under the planar platform of silicon.

6. Method, according to claim 1, wherein:

the support structure is 10–

100 nm wide and approximately 200 nm high.

7. Method, according to claim 1, wherein:

the support structure is in contact with the underside of the planar platform, leaving approximately 80% of an underside of the planar platform is exposed.

8. Method of forming a transistor comprising:

providing an SOI wafer comprising a handle substrate, a buried oxide layer (BOX) disposed atop the handle substrate and a silicon-on-insulator (SOI) layer disposed atop the buried oxide layer;

in a first etching step, patterning the SOI layer to become the active silicon layer of an SOI transistor, wherein a portion of the buried oxide layer is underneath the patterned SOI layer and other portions of the buried oxide layer are not underneath the patterned SOI layer, and wherein a top surface of the patterned SOI layer is exposed;

in a second etching step, etching the portions of the buried oxide layer which are not underneath the patterned SOI layer, thereby exposing a portion of a top surface of the handle substrate;

in a third etching step, removing the buried oxide layer from under the patterned SOI layer to form a standoff structure, thereby exposing a portion of a bottom surface of the patterned SOI layer,

performing gate oxidation, thereby forming gate oxide on the exposed surfaces of the patterned SOI layer;

depositing gate electrode material atop the handle substrate and covering the standoff structure as well as the patterned SOI layer; and

in a fourth etching step, etching the gate electrode material to form at least one gate stack atop the patterned SOI layer.

9. Method, according to claim 8, further comprising:

in a fifth etching step, etching the gate electrode material to form a back gate beneath the patterned SOI layer.

10. Method, according to claim 8, wherein:

the back gate is aligned with the at least one gate stack.

11. Method, according to claim 8, wherein:

the third etching step exposes a substantial portion of the underside of the patterned SOI layer.

12. Method, according to claim 8, wherein:

the third etching step exposes approximately 80% of the underside of the patterned SOI layer.

13. Method, according to claim 8, wherein:

the third etching step exposes additional portions of the handle substrate.

14. Method, according to claim 8, wherein:

during gate oxidation, gate oxide is also formed on the exposed surface of the handle substrate.

15. Method, according to claim 8, further comprising:

prior to the fourth etching step, depositing a hard mask material on top of the gate electrode material;

defining the hard mask material;

then performing the fourth etching step;

then removing the hard mask.

16. Method, according to claim 8, wherein:

the gate stack is etched in the fourth etching step using an anisotropic dry etch that is selective to the gate oxide.

17. Method, according to claim 8, wherein:

in the fourth etching step, the gate electrode material is etched down to approximately the level of the top surface of the patterned SOI layer, thereby creating electrode structures atop the patterned SOI layer and isolated therefrom by gate oxide.