Power supply circuit, voltage conversion circuit, semiconductor device, display device, display panel, and electronic equipment

• US 7,106,319 B2
• Filed: 09/10/2002
• Issued: 09/12/2006
• Est. Priority Date: 09/14/2001
• Status: Expired due to Fees

• Current Assignee: Seiko Epson Corporation (Seiko Group)
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Ishiyama, Hisanobu
• Primary Examiner(s): Hjerpe, Richard
• Assistant Examiner(s): Shapiro, Leonid
• Application Number:
  US10/237,684
• Publication Number:
  US 20030053321A1
• Time in Patent Office: 1,463 Days
• Field of Search: 345/211, 345204-205, 345/92, 345/87
• US Class Current: 345/211
• CPC Class Codes: G09G 2320/0276 for the purpose of adaptation to the characteristics of a display device, i.e. gamma correction
• CPC Class Codes: G09G 2330/02 Details of power systems and of start or stop of display operation
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: G09G 3/3688 suitable for active matrices only

Abstract

A power supply circuit which generates a power supply for a circuit which drives a source electrode and a gate electrode provided in a display, includes a first booster circuit which outputs a third potential boosted based on a difference between first and second potentials, a potential regulator circuit which outputs a fourth potential being a constant potential generated based on a difference between the first and third potentials, and a second booster circuit which outputs a fifth potential boosted based on a difference between the first and fourth potentials. The first and fourth potentials are supplied to a source electrode driver circuit, and the first and fifth potentials are supplied to a gate electrode driver circuit. A voltage supplied to the gate electrode driver circuit may be generated by using a voltage conversion circuit. The voltage conversion circuit includes a capacitor which capacitively couples a sixth power supply line to which a negative constant potential based on a first potential is supplied and a node to which a polarity inversion timing signal of a common electrode is supplied, a negative power supply generating circuit which generates a negative output potential based on a booster potential which is the difference between a regulating potential and the first potential, and a switching element connected between the negative power supply generating circuit and the sixth power supply line. A timing signal and a switching control signal of the switching element change in synchronization with each other.

Claims

1. A power supply circuit which generates a power supply for a circuit which drives a source electrode and a gate electrode provided in a display, comprising:

a first booster circuit which is connected with first and second power supply lines, which respectively supply first and second potentials, and supplies a third potential which is boosted based on a difference between the first and second potentials to a third power supply line;

a potential regulator circuit which is connected with the first and third power supply lines and supplies a fourth potential, which is a constant potential generated based on a difference between the first and third potentials, to a fourth power supply line; and

a second booster circuit which is connected with the first and fourth power supply lines and supplies a fifth potential, which is boosted based on a difference between the first and fourth potentials, to a fifth power supply line,

wherein at least the fourth potential is supplied to a source electrode driver circuit which drives the source electrode, and

wherein at least the fifth potential is supplied to a gate electrode driver circuit which drives the gate electrode,

the source electrode driver circuit with which the first and fourth power supply lines are connected;

a voltage conversion circuit with which the first and fifth power supply lines are connected and which supplies a sixth potential generated based on a difference between the first and second potentials to a sixth power supply line; and

the gate electrode driver circuit with which the first, fifth, and sixth power supply lines are connected,

wherein the voltage conversion circuit includes

a p-type transistor, a source terminal of which is connected with the first potential;

a first capacitor which capacitively couples a first node to which a first booster clock is supplied and a gate terminal of the p-type transistor;

a first level shifter which is connected between the source terminal of the p-type transistor and the gate terminal of the p-type transistor;

an n-type transistor, a drain terminal of which is connected with a drain terminal of the p-type transistor, and a source terminal of which is connected with a second node;

a second capacitor which capacitively couples the first potential and the second node;

a third capacitor which capacitively couples a third node to which a second booster clock is supplied and a gate terminal of the n-type transistor;

a second level shifter which is connected between the source terminal of the n-type transistor and the gate terminal of the n-type transistor; and

a fourth capacitor which capacitively couples a fourth node to which a given potential is supplied and the drain terminal of the n-type transistor,

wherein the first booster clock falls after the second booster clock has fallen, and the second booster clock rises after the first booster clock has risen,

wherein the potential supplied to the fourth node changes to a fifth potential, which is positive based on the first potential, in synchronization with fall of the first booster clock, and changes to the first potential in synchronization with rise of the second booster clock, and

wherein the source terminal of the n-type transistor is connected with the sixth power supply line.

2. A power supply circuit which generates a power supply for a circuit which drives a source electrode and a gate electrode provided in a display, comprising:

a first booster circuit which is connected with first and second power supply lines, which respectively supply first and second potentials, and supplies a third potential which is boosted based on a difference between the first and second potentials to a third power supply line;

a potential regulator circuit which is connected with the first and third power supply lines and supplies a fourth potential, which is a constant potential generated based on a difference between the first and third potentials, to a fourth power supply line; and

a second booster circuit which is connected with the first and fourth power supply lines and supplies a fifth potential, which is boosted based on a difference between the first and fourth potentials, to a fifth power supply line,

wherein at least the fourth potential is supplied to a source electrode driver circuit which drives the source electrode,

wherein at least the fifth potential is supplied to a gate electrode driver circuit which drives the gate electrode, and

the source electrode driver circuit with which the first and fourth power supply lines are connected;

a voltage conversion circuit with which the first and fifth power supply lines are connected and which supplies a sixth potential generated based on a difference between the first and second potentials to a sixth power supply line; and

the gate electrode driver circuit with which the first, fifth, and sixth power supply lines are connected,

wherein the voltage conversion circuit includes

a fifth capacitor which capacitively couples a fifth node to which a timing signal changing between given potentials is supplied and the sixth power supply line;

a negative power supply generating circuit which generates a sixth potential which is negative based on the first potential based on a difference between the first and fifth potentials; and

a switching element which is inserted between a node to which the sixth potential generated by the negative power supply generating circuit is supplied and the sixth power supply line, and controlled based on a given switching control signal,

wherein the timing signal and the switching control signal change in synchronization with each other.

3. The display device as defined in claim 2,

wherein the switching element is an n-type switching transistor,

wherein the negative power supply generating circuit comprises:

a p-type transistor, a source terminal of which is connected with the first potential;

a first capacitor which capacitively couples a first node to which a first booster clock is supplied and a gate terminal of the p-type transistor;

a first level shifter which is connected between the source terminal of the p-type transistor and the gate terminal of the p-type transistor;

an n-type transistor, a drain terminal of which is connected with a drain terminal of the p-type transistor, and a source terminal of which is connected with a second node;

a second capacitor which capacitively couples the first potential and the second node;

a third capacitor which capacitively couples a third node to which a second booster clock is supplied and a gate terminal of the n-type transistor;

a second level shifter which is connected between the source terminal of the n-type transistor and the gate terminal of the n-type transistor; and

a fourth capacitor which capacitively couples a fourth node to which a given potential is supplied and the drain terminal of the n-type transistor,

wherein the first booster clock falls after the second booster clock has fallen, and the second booster clock rises after the first booster clock has risen,

wherein the potential supplied to the fourth node changes to a fifth potential, which is positive based on the first potential, in synchronization with fall of the first booster clock, and changes to the first potential in synchronization with rise of the second booster clock, and

wherein the source terminal of the n-type transistor is connected with the sixth power supply line through the n-type switching transistor.

4. A power supply circuit which generates a power supply for a circuit which drives a source electrode and a gate electrode provided in a display, comprising:

a first booster circuit which is connected with first and second power supply lines, which respectively supply first and second potentials, and supplies a third potential which is boosted based on a difference between the first and second potentials to a third power supply line;

a potential regulator circuit which is connected with the first and third power supply lines and supplies a fourth potential, which is a constant potential generated based on a difference between the first and third potentials, to a fourth power supply line; and

a second booster circuit which is connected with the first and fourth power supply lines and supplies a fifth potential, which is boosted based on a difference between the first and fourth potentials, to a fifth power supply line,

wherein at least the fourth potential is supplied to a source electrode driver circuit which drives the source electrode, and

wherein at least the fifth potential is supplied to a gate electrode driver circuit which drives the gate electrode, and

the source electrode driver circuit with which the first and fourth power supply lines are connected;

an external component connection terminal of the power supply circuit which is disposed on a second side opposite to a first side of the semiconductor device on which an electrode for driving the source electrode is disposed; and

a terminal, with which the fifth power supply line is connected, is disposed on at least one of a third side and a fourth side of the semiconductor device which intersect the first and second sides.

5. A power supply circuit which generates a power supply for a circuit which drives a source electrode and a gate electrode provided in a display, comprising:

a first booster circuit which is connected with first and second power supply lines, which respectively supply first and second potentials, and supplies a third potential which is boosted based on a difference between the first and second potentials to a third power supply line;

a potential regulator circuit which is connected with the first and third power supply lines and supplies a fourth potential, which is a constant potential generated based on a difference between the first and third potentials, to a fourth power supply line; and

a second booster circuit which is connected with the first and fourth power supply lines and supplies a fifth potential, which is boosted based on a difference between the first and fourth potentials, to a fifth power supply line,

wherein at least the fourth potential is supplied to a source electrode driver circuit which drives the source electrode, and

wherein at least the fifth potential is supplied to a gate electrode driver circuit which drives the gate electrode, and

the source electrode driver circuit with which the first and fourth power supply lines are connected; and

a plurality of the source electrodes including a first to k-th and (k+1)th to Nth source electrodes (1≦

k<

N, k is a natural number);

a first RAM which stores display data for driving the first to k-th source electrodes; and

a second RAM which stores display data for driving the (k+1)th to Nth source electrodes,

wherein the power supply circuit is disposed in a region between the first RAM and the second RAM.