Method for increasing dynamic range of a pixel by multiple incomplete reset

• US 7,106,373 B1
• Filed: 12/14/1999
• Issued: 09/12/2006
• Est. Priority Date: 02/09/1998
• Status: Expired due to Fees

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Dierickx, Bart
• Primary Examiner(s): Vu, Ngoc-Yen
• Assistant Examiner(s): Whipkey, Jason
• Application Number:
  US09/460,473
• Time in Patent Office: 2,464 Days
• Field of Search: 250/208.1, 250/214.R, 348/294, 348/296, 348/297, 348299-302, 348307-311, 348/314
• US Class Current: 348/308
• CPC Class Codes: G01J 1/44 Electric circuits for command of an exposure part G03B7/02
• CPC Class Codes: H04N 25/571 involving a non-linear response
• CPC Class Codes: H04N 25/573 the logarithmic type
• CPC Class Codes: H04N 25/575 with a response composed of multiple slopes
• CPC Class Codes: H04N 3/155 Control of the image-sensor operation, e.g. image processing within the image-sensor

Abstract

A method is disclosed for obtaining a read-out signal of a pixel having at least a photosensitive element with a charge storage node. Charge carriers are converted from radiation impinging on the photosensitive element. While acquiring charge carriers on said charge storage node, after a time period at least one reset pulse with a predetermined amplitude is applied on said charge storage node, said pulse resetting incompletely the charge carriers acquired at the moment of applying said pulse; and thereafter charge carriers are further acquired on said charge storage node.

Claims

1. A method for obtaining a read-out signal of a pixel having at least a photosensitive element and a charge storage node, the method comprising the steps of while acquiring charge carriers on said charge storage node, said charge carriers being converted from radiation impinging on the photosensitive element:

after a time period applying at least one reset pulse with a predetermined amplitude on said charge storage node, said pulse resetting incompletely the charge carriers acquired at the moment of applying said pulse thereby partially discharging the charge storage node; and

thereafter

further acquiring charge carriers on said charge storage node.

2. The method as recited in claim 1 wherein a plurality of reset pulses is applied on said charge storage node.

3. The method as recited in claim 2 wherein at least two of said plurality of reset pulses have a different amplitude.

4. The method as recited in claim 1 further comprising the step of applying a reference signal on said charge storage node whereon said reset pulse is superposed.

5. The method as recited in claim 1 wherein said reset pulse is delivered by a reset transistor, said reset transistor being in series with said photosensitive element.

6. The method as recited in claim 1 wherein said photosensitive element has an output node, said charge storage node being the output node of said photosensitive element.

7. The method as recited in claim 6 wherein said photosensitive element has a parasitic capacitor and wherein said charge storage node is the parasitic capacitor of the photosensitive element.

8. The method as recited in claim 1 wherein said pixel further comprises an amplifying element directly or indirectly connected to said charge storage node, the amplifying element amplifying or buffering the signal on said charge storage node for further signal processing.

9. The method as recited in claim 1 wherein the read-out signal is function of a combination of charges acquired prior and after the application of said reset pulses.

10. The method as recited in claim 1 wherein said pixel is implemented in a MOS technology.

11. The method as recited in claim 1 further comprising the step of applying a prior reset pulse on said charge storage node, prior to the step of acquiring charge carriers on said charge storage node.

12. The method as recited in claim 11 wherein during the time of application of said prior reset pulse and during the time of application of said reset pulse on said charge storage node, acquisition of charge carriers is blocked.

13. The method as recited in claim 11 wherein said prior reset pulse is forcing a voltage on said charge storage node and wherein during the time of application of said prior reset pulse on said charge storage node, acquisition of charge carriers is blocked.