Wireless communications systems and methods for direct memory access and buffering of digital signals for multiple user detection

• US 7,110,437 B2
• Filed: 03/14/2002
• Issued: 09/19/2006
• Est. Priority Date: 03/14/2001
• Status: Active Grant

• Current Assignee: Mercury Systems, Incorporated
• Original Assignee: Mercury Computer Systems Incorporated
• Inventors: Majchrzak, David E., Jacques, Kathleen J., Dunn, Ian N., Jenkins, William J., Lauginiger, Frank P., Cantrell, Paul E., Oates, John H., Fuchs, Alden J., Imperiali, Steven R., Vinskus, Michael J., Cifric, Mirza, Greene, Jonathan E.
• Primary Examiner(s): Bocure, Tesfaldet
• Application Number:
  US10/099,889
• Publication Number:
  US 20030191887A1
• Time in Patent Office: 1,650 Days
• Field of Search: 709/22, 709/23, 709/24, 710/212, 710/200, 710/22, 710/23, 710/24, 375130-153, 711/212, 711/200
• US Class Current: 375/147
• CPC Class Codes: H04B 1/707 using direct sequence modulation
• CPC Class Codes: H04B 1/7093 Matched filter type
• CPC Class Codes: H04B 1/7105 Joint detection techniques, e.g. linear detectors
• CPC Class Codes: H04B 1/71052 using decorrelation matrix
• CPC Class Codes: H04B 1/71075 Parallel interference cancellation
• CPC Class Codes: H04B 1/7115 Constructive combining of multi-path signals, i.e. RAKE receivers
• CPC Class Codes: H04B 2201/70707 Efficiency-related aspects
• CPC Class Codes: H04B 2201/70711 with modular structure

Abstract

The invention provides methods and apparatus for multiple user detection (MUD) processing that have application, for example, in improving the capacity CDMA and other wireless base stations. One aspect of the invention provides a digital signal processor (“DSP”) that processes user waveforms. The DSP has an associated memory and an associated direct memory access (“DMA”) controller that controls access to that memory. A programmable logic device (“PLD”) is coupled to the DMA controller and configures it to move data relating to user waveform characteristics from the memory to a buffer external to the DSP.

Claims

1. A communications device for detecting user transmitted symbols encoded in spread spectrum waveforms (hereinafter “

user waveforms”

) comprising

a digital signal processor (hereinafter “

DSP”

) that processes user waveforms to determine characteristics thereof, the DSP having an associated memory and an associated direct memory access (hereinafter “

DMA”

) controller that controls access to that memory, and

a programmable logic device (hereinafter “

PLD”

) that is coupled to the DMA controller and that configures it to move data relating to user waveform characteristics from the memory to a buffer external to the DSP,

wherein said user waveform characteristics comprise one or more waveform amplitudes.

2. The device of claim 1, wherein the PLD configures the DMA controller to move the data from the memory to the buffer in blocks.

3. The device of claim 2, wherein the PLD configures the DMA controller to move the data from the memory to the buffer in unfragmented blocks.

4. The device of claim 2, wherein the PLD configures the DMA controller to move the data from the memory to the buffer in fragmented blocks.

5. The device of claim 4, wherein the PLD formats the fragmented blocks in the buffer for subsequent defragmentation.

6. The device of claim 1, wherein said waveform characteristics further comprise amplitude ratios of said user waveforms.

7. A communications device for detecting user transmitted symbols encoded in spread spectrum waveforms (hereinafter “

user waveforms”

) comprising

a first-in first-out buffer comprising a dual-port random access memory,

a digital signal processor (hereinafter “

DSP”

) that processes user waveforms to determine characteristics thereof, the DSP having an associated memory and an associated direct access memory (hereinafter “

DMA”

) controller that controls access to that memory,

a programmable logic device (hereinafter “

PLD”

) that is coupled to the DMA controller and that configures it to move data relating to user waveform characteristics from the memory to the buffer external to the DSP,

wherein said user waveform characteristics comprise one or more waveform amplitudes.

8. The device of claim 7, wherein the programmable logic device is any of a field programmable gate array and a applications specific integrated circuit.

9. The device of claim 7, comprising a multi-port data switch coupled with the PLD.