Phase sampling techniques using amplitude bits for digital receivers

• US 7,113,552 B1
• Filed: 12/21/2001
• Issued: 09/26/2006
• Est. Priority Date: 12/21/2000
• Status: Expired due to Term

• Current Assignee: CSR Technology Incorporated (Qualcomm, Inc.)
• Original Assignee: SIRF Technology Incorporated (Qualcomm, Inc.)
• Inventors: Cahn, Charles R., Norman, Charles P.
• Primary Examiner(s): TRAN, KHANH C
• Application Number:
  US10/036,788
• Time in Patent Office: 1,740 Days
• Field of Search: 375/147, 375/148, 375/316, 375/340, 375324-325, 342/357.06, 342/357.12, 342/417, 342/458, 342/463
• US Class Current: 375/316
• CPC Class Codes: G01S 19/21 Interference related issues ; Issues related to cross-correlation, spoofing or other methods of denial of service
• CPC Class Codes: G01S 19/24 Acquisition or tracking or demodulation of signals transmitted by the system synchronisation aspects of direct sequence spread spectrum modulation H04B1/7073
• CPC Class Codes: G01S 19/29 carrier including Doppler, related G01S19/246 takes precedence
• CPC Class Codes: H03D 7/16 Multiple-frequency-changing
• CPC Class Codes: H04L 27/2337 using digital techniques to measure the time between zero-crossings
• CPC Class Codes: H04L 27/2338 using sampling H04L27/2331 - H04L27/2335 take precedence

Abstract

The present invention uses at least one amplitude bit to assist the phase-sampling technique used in digital receiver architectures. For digital receivers where the Intermediate Frequency (IF) is an integer multiple of the fundamental frequency f_o, the present invention provides reduced processing complexity and reduced power consumption. The present invention allows the digital receiver to avoid performing coordinate rotation at high speeds, and replaces such a coordinate rotation with a simple phase subtraction. This replacement of the coordinate rotation allows the receiver to use a less complicated design, and to consume less power as a result.

Claims

1. A method for phase sampling an incoming signal in a digital receiver, comprising:

downconverting the incoming signal to an Intermediate Frequency (IF) signal;

running a counter at a higher frequency than that of the Intermediate Frequency (IF) signal;

outputting a state of the counter when the IF signal has a zero crossing,

outputting a state of a magnitude of the IF signal when the IF signal has a zero crossing; and

extracting the phase of the IF signal from the outputted state of the counter and the outputted state of the magnitude.

2. The method of claim 1, wherein the digital receiver is a Global Positioning System (GPS) receiver.

3. The method of claim 2, wherein the phase extraction is performed by subtracting an estimated phase from the extracted phase of the IF signal.

4. The method of claim 3, wherein the counter is running at a frequency that is an integer multiple of the IF.

5. A method for phase sampling an incoming signal in a digital Global Positioning System (GPS) receiver, comprising:

downconverting the incoming signal to an Intermediate Frequency (IF) signal;

running a counter at a higher frequency than that of the Intermediate Frequency (IF) signal and at an integer multiple of the IF;

outputting a state of the counter when the IF signal has a zero crossing,

outputting a state of a magnitude of the IF signal when the IF signal has a zero crossing; and

extracting the phase of the IF signal from the outputted state of the counter and the outputted state of the magnitude, wherein the phase extraction is performed by subtracting an estimated phase from the extracted phase of the IF signal and the extracted phase of the IF signal is given by;

−

2π

J/M radians,

where M is the integer multiple of the IF, and J is the outputted state of the counter.

6. The method of claim 5, wherein the state of the magnitude of the IF signal is a digital state.

7. The method of claim 6, wherein the digital state is at least two bits.

8. A method for phase sampling an incoming signal in a digital receiver, comprising:

downconverting the incoming signal to an Intermediate Frequency (IF) signal;

running a counter at a higher frequency than that of the Intermediate Frequency (IF) signal;

holding a state of the counter when the IF signal has a zero crossing;

holding a magnitude bit that is set to 1 if an absolute value of the IF signal exceeded a threshold prior to an occurrence of a previous zero crossing; and

extracting the phase of the IF signal from the state of the counter and the state of the magnitude bit.