Active matrix display device

• US 7,116,298 B2
• Filed: 06/24/2004
• Issued: 10/03/2006
• Est. Priority Date: 10/20/2000
• Status: Expired due to Term

• Current Assignee: Panasonic Liquid Crystal Display Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Hitachi Device Engineering Co., Ltd. (Hitachi, Ltd.), Hitachi, Ltd.
• Inventors: Hasegawa, Atsushi, Miyazawa, Toshio, Goto, Kazutaka, Takemoto, Iwao, Maki, Masashiro
• Primary Examiner(s): Osorio, Ricardo
• Assistant Examiner(s): Said, Mansour M.
• Application Number:
  US10/874,357
• Publication Number:
  US 20040246227A1
• Time in Patent Office: 831 Days
• Field of Search: 345/87, 345/90, 345/91, 345/94, 345/98, 345/99, 345/100, 345/102, 345204-206, 345/208, 345/210, 345/211, 345/214, 349/42, 349/151
• US Class Current: 345/87
• CPC Class Codes: G09G 2300/0408 Integration of the drivers onto the display substrate
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 3/36 using liquid crystals
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: G09G 3/3659 the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: G09G 3/3688 suitable for active matrices only
• CPC Class Codes: G09G 3/3696 Generation of voltages supplied to electrode drivers
• CPC Class Codes: G09G 5/39 Control of the bit-mapped memory
• CPC Class Codes: G11C 19/184 with field-effect transistors, e.g. MOS-FET
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor

Abstract

A display device includes a dynamic ratioless shift register which is operated in a stable manner and can expand the degree of freedom of design. In the dynamic ratioless shift register which is provided with thin film transistors having semiconductor layers made of p-Si on a substrate surface, a node which becomes the floating state is connected to a fixed potential through a capacitance element.

Claims

1. A display device being provided with a display driving circuit including a dynamic shift register which includes a first MISTFT on a substrate surface, wherein:

the dynamic shift register is comprised of a second MISTFT and a third MISTFT which use polycrystalline silicon as a semiconductor layer;

the first MISTFT includes a gate electrode, a first electrode and a second electrode, wherein a voltage of the gate electrode is boosted by a voltage of the first electrode changing from low level to high level,

the second MISTFT is connected between a ground level line and the gate electrode of the first MISTFT, and

the third MISTFT is comprised such that the gate electrode of the first MISTFT is dropped to a ground level during a period other than a period in which a signal of high level is transmitted into the gate electrode of the first MISTFT.

2. A display device according to claim 1,

wherein the dynamic shift register includes a connection of a plurality of stages, each stage including the first MISTFT, the second MISTFT, and the third MISTFT, and wherein an output signal from a preceding stage of said plurality of stages is input into the third MISTFT of a next stage of said plurality of stages.

3. A display device according to claim 1,

wherein the dynamic shift register includes a connection of a plurality of stages, each stage including the first MISTFT, the second MISTFT, and the third MISTFT, wherein a first synchronous pulse is input into the first MISTFT of a preceding stage of said plurality of stages, and wherein a second synchronous pulse is input into the first MISTFT of a next stage of said plurality of stages.