System and method for lithography simulation

• US 7,117,478 B2
• Filed: 01/18/2005
• Issued: 10/03/2006
• Est. Priority Date: 10/07/2003
• Status: Active Grant

• Current Assignee: ASML Netherlands BV (ASML Holding NV)
• Original Assignee: Brion Technologies Incorporated (ASML Holding NV)
• Inventors: Ye, Jun, Chen, Luoqi, Chen, Xun, Lu, Yen-Wen, Cao, Yu
• Primary Examiner(s): Kik, Phallaka
• Application Number:
  US11/037,988
• Publication Number:
  US 20050122500A1
• Time in Patent Office: 623 Days
• Field of Search: 716/21, 430/5, 378/35, 700/97, 700/120, 700/121, 250/492.22
• US Class Current: 716/51
• CPC Class Codes: G03F 1/00 Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
• CPC Class Codes: G03F 7/004 Photosensitive materials G03F7/12, G03F7/14 take precedence
• CPC Class Codes: G03F 7/705 Modelling or simulating from physical phenomena up to complete wafer processes or whole workflow in wafer productions
• CPC Class Codes: G03F 7/70666 Aerial image, i.e. measuring the image of the patterned exposure light at the image plane of the projection system
• CPC Class Codes: G06F 2119/18 Manufacturability analysis or optimisation for manufacturability
• CPC Class Codes: G06F 30/20 Design optimisation, verification or simulation optimisation, verification or simulation of circuit designs G06F30/30
• CPC Class Codes: G06F 30/333 Design for testability [DFT], e.g. scan chain or built-in self-test [BIST]
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: G06T 2207/30148 Semiconductor; IC; Wafer
• CPC Class Codes: G06T 7/0004 Industrial image inspection
• CPC Class Codes: G16Z 99/00 Subject matter not provided for in other main groups of this subclass
• CPC Class Codes: G21K 5/00 Irradiation devices discharge tubes for irradiating H01J37/00

Abstract

There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a technique of, and system for simulating, verifying, inspecting, characterizing, determining and/or evaluating the lithographic designs, techniques and/or systems, and/or individual functions performed thereby or components used therein. In one embodiment, the present invention is a system and method that accelerates lithography simulation, inspection, characterization and/or evaluation of the optical characteristics and/or properties, as well as the effects and/or interactions of lithographic systems and processing techniques. In this regard, in one embodiment, the present invention employs a lithography simulation system architecture, including application-specific hardware accelerators, and a processing technique to accelerate and facilitate verification, characterization and/or inspection of a mask design, for example, RET design, including detailed simulation and characterization of the entire lithography process to verify that the design achieves and/or provides the desired results on final wafer pattern. The system includes: (1) general purpose-type computing device(s) to perform the case-based logic having branches and inter-dependency in the data handling and (2) accelerator subsystems to perform a majority of the computation intensive tasks.

Claims

1. A method of inspecting a first marginal area of a design on or in a photomask, the method comprising:

evaluating a response of a lithographic design on wafer to a change in at least one process parameter of a photolithographic process to determine the first marginal area, including;

generating a pixel-based bitmap representation of the lithographic design, wherein the pixel-based bitmap includes pixel data, and wherein the lithographic design includes at least a portion that is associated with the first marginal area of the design on or in the photomask;

generating a first simulated image of the lithographic design on wafer using (1) the pixel-based bitmap representation of the lithographic design and (2) a first relationship representing an imaging path of projection and illumination optics of the photolithographic process, wherein the photolithographic process uses photolithographic equipment;

generating a second simulated image of the lithographic design on wafer using (1) the pixel-based bitmap representation of the lithographic design and (2) a second relationship representing an imaging path of projection and illumination optics of the photolithographic process;

wherein a difference between (I) the first relationship representing the imaging path of the projection and illumination optics of the photolithographic process and (ii) the second relationship representing the imaging path of the projection and illumination optics of the photolithographic process includes the change in the at least one process parameter of the photolithographic process; and

determining the first marginal area of the lithographic design using the first simulated image and the second simulated image;

inspecting the first marginal area of the design on or in the photomask using at least one metrology or inspection tool.

2. The method of claim 1, wherein the lithographic design includes resolution enhancement technology.

3. The method of claim 1, wherein inspecting the first marginal area of a design on or in a photomask includes generating an aerial image of the first marginal ama at a wafer plane of projection and illumination optics of the photolithographic process.

4. The method of claim 1, wherein:

determining the first marginal area of the lithographic design using the first simulated image and the second simulated image includes determining a critical dimension sensitivity of the lithographic design on wafer to the change in the at least one process parameter of the photolithographic process; and

wherein inspecting the first marginal area of the design on or in the photomask includes generating an aerial image of the first marginal area to determine the critical dimension of the design on or in the photomask at a wafer plane of projection and illumination optics of the photolithographic process.

5. The method of claim 4, wherein determining the critical dimension sensitivity of the lithographic design to the change in the at least one process parameter of the photolithographic process further includes determining a plurality of derivatives as the critical dimension sensitivity of the lithographic design.

6. The method of claim 1, wherein the change in the at least one process parameter of the photolithographic process is a change in focus, illumination dose, numerical aperture or illumination aperture of the photolithographic equipment.

7. The method of claim 1, wherein the lithographic design is a localized region of an integrated circuit design.

8. The method of claim 1, further including determining a configuration of settings of the photolithographic equipment using the evaluation of the response of the lithographic design on wafer to the change in the at least one process parameter of the photolithographic process.

9. The method of claim 1, further including determining lithography settings using the evaluation of the response of the lithographic design on wafer to the change in the at least one process parameter of the photolithographic process.

10. The method of claim 1, wherein the first and second relationships representing the imaging path of the projection and illumination optics are coefficient matrices representing the imaging path of the projection and illumination optics of the photolithographic equipment.

11. The method of claim 10, wherein each coefficient matrix is representative of one or more of a focus, dose, numerical aperture, illumination aperture, and aberration of the photolithographic equipment.

12. The method of claim 1, wherein the change in the at least one process parameter of the photolithographic process is a change in a bias or an error in a critical dimension of a photomask containing the lithographic design.

13. The method of claim 1, wherein the lithographic design includes at least a portion that is associated with a second marginal area of the design on or in the photomask and wherein the method further includes:

determining the second marginal area of the design on or in the photomask by;

generating a first developed resist simulated image of the lithographic design on wafer using (1) the pixel-based bitmap representation of the lithographic design, (2) the first relationship representing the imaging path of the projection and illumination optics of the photolithographic process, and (3) a model of a resist;

generating a second developed resist simulated image of the lithographic design on a wafer using (1) the pixel-based bitmap representation of the lithographic design, (2) the second relationship representing the imaging path of the projection and illumination optics of the photolithographic process, and (3) the model of the resist;

determining the second marginal area of the lithographic design using the first developed resist simulated image and the second developed resist simulated image; and

inspecting the second marginal area of the design on or in the photomask using at least one metrology or inspection tool.

14. The method of claim 13, wherein:

determining the second marginal area of the lithographic design using the first developed resist simulated image and the second developed resist simulated image includes determining a critical dimension sensitivity of the lithographic design to the change in the at least one process parameter of the photolithographic process; and

inspecting the second marginal area of the design on or in the photomask includes generating an SEM image of the second marginal area after wafer printing to determine a critical dimension of the design after wafer printing.

15. The method of claim 13, wherein the model of the resist simulates or emulates physical and chemical processes of resist development.

16. The method of claim 13, wherein the first and second developed resist simulated images each includes a representation of developed resist edge locations.

17. The method of claim 13, wherein the first and second developed resist simulated images are representative of a developed resist edge profile.

18. The method of claim 13, wherein the lithographic design on wafer includes at least a portion that is associated with a third marginal area of the design on or in the photomask and wherein the method further includes:

determining the third marginal area of the design on or in the photomask by;

generating a first etch simulated image using;

(1) the first developed resist simulated image of the lithographic design on wafer, and (2) an etching process model;

generating a second etch simulated image using;

(1) the second developed resist simulated image of the lithographic design on wafer, and (2) the etching process model; and

determining the third marginal area of the lithographic design using the first etch simulated image and the second etch simulated image; and

inspecting the third marginal area of the design on or in the photomask using at least one metrology or inspection tool.

19. The method of claim 18, wherein inspecting the third marginal area of the design on or in the photomask includes using an SEM inspection tool.

20. The method of claim 18, wherein:

determining the third marginal area of the lithographic design using the first etch simulated image and the second etch simulated image includes determining a critical dimension sensitivity of the lithographic design on wafer to the change in the at least one process parameter of the photolithographic process; and

wherein inspecting the third marginal area of the design on or in the photomask includes generating an SEM image of the third marginal area after wafer printing to determine a critical dimension of the design after wafer printing.

21. The method of claim 13, wherein the change in the at least one process parameter of the photolithographic process is a change in a bias or an error in a critical dimension of a photomask containing the lithographic design.

22. The method of claim 21, wherein the change in bias is a difference between a linewidth and a predetermined design value.

23. The method of claim 21, wherein the change in bias is due to resist over-development or under-development on the photomask.

24. The method of claim 23, wherein the resist over-development or under-development is dependent on a linewidth or patterns of the lithographic design.

25. A method of inspecting a first marginal area of a design on or in a photornask, the method comprising:

evaluating a response of a lithographic design on wafer to a change in at least one process parameter of a photolithographic process to determine the first marginal area, including;

generating a pixel-based bitmap representation of the lithographic design, wherein the pixel-based bitmap includes pixel data, and wherein the lithographic design includes at least a portion that is associated with the first marginal area of the design on or in the photomask;

generating a first developed resist simulated image of the lithographic design on wafer using (1) the pixel-based bitmap representation of the lithographic design, (2) a first relationship representing an imaging path of projection and illumination optics of the photolithographic process, and (3) a model of a resist, wherein the photolithographic process uses photolithographic equipment;

generating a second developed resist simulated image of the lithographic design on wafer using (1) the pixel-based bitmap representation of the lithographic design, (2) a second relationship representing a imaging path of projection and illumination optics of the photolithographic process, and (3) the model of the resist;

wherein a difference between (i) the first relationship representing the imaging path of the projection and illumination optics of the photolithographic process and (ii) the second relationship representing the imaging path of the projection and illumination optics of the photolithographic process includes the change in the at least one process parameter of the photolithographic process; and

determining the first marginal area of the lithographic design using the first developed resist simulated image and the second developed resist simulated image; and

inspecting the first marginal area of the design on or in the photomask using at least one metrology or inspection tool.

26. The method of claim 25, wherein:

determining the first marginal area of the lithographic design using the first developed resist simulated image and the second developed resist simulated image includes determining a critical dimension sensitivity of the lithographic design to the change in the at least one process parameter of the photolithographlc process; and

wherein inspecting the first marginal area of the design on or in the photomask includes generating an SEM image of the first marginal area after wafer printing to determine a critical dimension of the design after wafer printing.

27. The method of claim 25, wherein the lithographic design includes resolution enhancement technology.

28. The method of claim 25, wherein the model of the resist simulates or emulates physical and chemical processes of resist development.

29. The method of claim 25, wherein the first and second developed resist simulated images each includes a representation of developed resist edge locations.

30. The method of claim 25, wherein the first and second developed resist simulated images are representative of a developed resist edge profile.

31. The method of claim 25, wherein the change in the at least one process parameter of the photolithographic process is a change in focus, illumination dose, numerical aperture or illumination aperture of the photolithographic equipment.

32. The method of claim 25, wherein the lithographic design is a localized region of an integrated circuit design.

33. The method of claim 25, wherein the lithographic design on wafer includes at least a portion that is associated with a second marginal area of the design on or in the photomask and wherein the method further includes:

determining the second marginal area of the design on or in the photomask by;

generating a first etch simulated image using;

(1) the first developed resist simulated image of the lithographic design on wafer, and (2) an etching process model;

generating a second etch simulated image using;

(1) the second developed resist simulated image of the lithographic design on wafer, and (2) the etching process model; and

determining the second marginal area of the lithographic design using the first etch simulated image and the second etch simulated image; and

inspecting the second marginal area of the design on or in the photomask using at least one metrology or inspection tool.

34. The method of claim 33, wherein inspecting the second marginal area of the design on or in the photomask indudes using an SEM inspection tool.

35. The method of claim 33, wherein:

determining the second marginal area of the lithographic design using the first etch simulated image and the second etch simulated image includes determining a critical dimension sensitivity of the lithographic design on wafer to the change in the at least one process parameter of the photolithographic process; and

wherein inspecting the second marginal area of the design on or in the photomask includes generating an SEM image of the second marginal area after wafer printing to determine a critical dimension of the design after wafer printing.

36. The method of claim 25, wherein the change in the at least one process parameter of the photolithographic process is a change in a bias or an error in a critical dimension of a photomask containing the lithographic design.

37. The method of claim 36, wherein the change in bias is a difference between a linewidth and a predetermined design value.

38. The method of claim 36, wherein the change in bias is due to resist over-development or under-development on the photomask.

39. The method of claim 38, wherein the resist over-development or under-development is dependent on a linewidth or patterns of the lithographic design.

40. A method of inspecting a first marginal area of a design on or in a photomask, the method comprising:

evaluating a response of a lithographic design on wafer to a change in at least one process parameter of a photolithographic process to determine the first marginal area, including;

generating a pixel-based bitmap representation of the lithographic design, wherein the pixel-based bitmap includes pixel data, and wherein the lithographic design includes at least a portion that is associated with the first marginal area of the design on or in the photomeak;

generating a first etch simulated image of the lithographic design on wafer using (1) the pixel-based bitmap representation of the lithographic design, (2) a first relationship representing an imaging path of the projection and illumination optics of the photolithographic process, (3) a model of the a resist, and (4) an etching process model, wherein the photolithographic process uses photolithographic equipment;

generating a second etch simulated image of the lithographic design on wafer using (1) the pixel-based bitmap representation of the lithographic design, (2) a second relationship representing an imaging path of the projection and illumination optics of the photolithographic process, (3) the model of the resist, and (4) the etching process model;

wherein a difference between (i) the first relationship representing the imaging path of the projection and illumination optics of the photolithographic process and (ii) the second relationship representing the imaging path of the projection and illumination optics of the photolithographic process includes the change in the at least one process parameter of the photolithographic process; and

determining the first marginal area of the lithographic design using the first etch simulated image and the second etch simulated image; and

inspecting the first marginal area of the design on or in the photomask using at least one metrology or inspection tool.

41. The method of claim 40, wherein the lithographic design includes resolution enhancement technology.

42. The method of claim 40, wherein the model of the resist simulates or emulates physical and chemical processes of resist development.

43. The method of claim 40, wherein the first and second etch simulated images each includes a representation of an after-etch edge locations.

44. The method of claim 40, wherein the first and second etch simulated images are representative of an after-etch edge profile.

45. The method of claim 40, wherein the change in the at least one process parameter of the photolithographic process is a change in focus, illumination dose, numerical aperture or illumination aperture of the photolithographic equipment.

46. The method of claim 40, wherein the lithographic design is a localized region of an integrated circuit design.

47. The method of claim 40, wherein inspecting the first marginal area of the design on or in the photomask includes using an SEM inspection tool.

48. The method of claim 40, wherein:

determining the first marginal area of the lithographic design using the first etch simulated image and the second etch simulated image includes determining a critical dimension sensitivity of the lithographic design on wafer to the change in the at least one process parameter of the photolithographic process; and

wherein inspecting the first marginal area of the design on or in the photomask includes generating an SENT image of the first marginal area after wafer printing to determine a critical dimension of the design after wafer printing.

49. The method of claim 40, wherein the change in the at least one process parameter of the photolithographic process is a change in a bias or an error in a critical dimension of a photomask containing the lithographic design.

50. The method of claim 49, wherein the change in bias is a difference between a linewidth and a predetermined design value.

51. The method of claim 49, wherein the change in bias is due to resist over-development or under-development on the photomask.

52. The method of claim 51, wherein the resist over-development or under-development is dependent on a linewidth or patterns of the lithographic design.