SOI device with reduced drain induced barrier lowering

• US 7,122,411 B2
• Filed: 08/19/2004
• Issued: 10/17/2006
• Est. Priority Date: 08/31/2000
• Status: Expired due to Fees

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Mouli, Chandra V.
• Primary Examiner(s): Blum, David S.
• Application Number:
  US10/922,345
• Publication Number:
  US 20050020041A1
• Time in Patent Office: 789 Days
• Field of Search: 438/154, 438/194, 438/217, 438/459
• US Class Current: 438/154
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/26533 of electrically inactive species in silicon to make buried insulating layers
• CPC Class Codes: H01L 21/2658 of a molecular ion, e.g. decaborane
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

A CMOS device formed with a Silicon On Insulator (SOI) technology with reduced Drain Induced Barrier Lowering (DIBL) characteristics and a method for producing the same. The method involves a high energy, high dose implant of boron and phosphorus through the p- and n-wells, into the insulator layer, thereby creating a borophosphosilicate glass (BPSG) structure within the insulation layer underlying the p- and n-wells of the SOI wafer. Backend high temperature processing steps induce diffusion of the boron and phosphorus contained in the BPSG into the p- and n-wells, thereby forming a retrograde dopant profile in the wells. The retrograde dopant profile reduces DIBL and also provides recombination centers adjacent the insulator layer and the active layer to thereby reduce floating body effects for the CMOS device.

Claims

1. A method for fabricating an integrated circuit, comprising:

providing a substrate having a semiconductor layer overlying an insulating layer;

doping the insulating layer with electrical dopant; and

diffusing electrical dopant from the insulating layer out into the semiconductor layer by exposing the substrate to an elevated temperature, wherein a concentration of electrical dopant in the seminconductor layer defines a retrograde dopant profile after diffusing.

2. The method of claim 1, wherein, doping comprises implanting electrical dopant into isolated regions of the insulating layer.

3. The method of claim 2, wherein diffusing electrical dopant diffuses electrical dopant into isolated portions of the semiconductor layer overlying the isolated regions, wherein the concentration of electrical dopant defining the retrograde dopant profile is a concentration of dopant in the portions.

4. The method of claim 2, wherein doping comprises implanting n-type dopant into some desired isolated regions and implanting p-type dopant into other desired isolated regions of the insulating layer.

5. The method of claim 4, wherein the p-type dopant comprises phosphorus and the n-type dopant comprises boron.

6. The method of claim 5, wherein doping forms borophosphosilicate glass (BPSG) within the insulating layer.

7. The method of claim 1, further comprising forming transistor devices in the semiconductor layer directly over regions of the semiconductor layer containing electrical dopant diffused from the insulating layer.

8. The method of claim 7, wherein the transistor devices are complementary transistor devices.

9. The method of claim 8, wherein forming transistor devices comprises forming at least one each of a NMOS and a PMOS device.

10. The method of claim 9, wherein pairs of devices comprising a NMOS and a PMOS device form a CMOS device.

11. The method of claim 7, further comprising adjusting threshold voltages of the transistor devices.

12. The method of claim 11, wherein adjusting threshold voltages comprises implanting an other dopant in the semiconductor layer.

13. The method of claim 12, wherein implanting the other dopant comprises implantation using BF₂.

14. The method of claim 12, wherein the other dopant comprises arsenic.

15. The method of claim 1, wherein exposing the substrate to an elevated temperature comprises forming a passivation layer over the insulating layer.

16. The method of claim 1, wherein the concentration of the electrical dopant in desired regions is at least about 10²⁰/cm³.

17. The method of claim 16, wherein the concentration of the electrical dopant in the portions is at least about 9×

10¹⁷/cm³.

18. The method of claim 1, wherein the substrate is a Separation by IMplanted OXygen (SIMOX) wafer.

19. The method of claim 1, wherein the insulating layer comprises a buried silicon dioxide layer.

20. The method of claim 1, wherein the semiconductor layer is an epitaxial silicon layer.

21. A method for forming an integrated circuit, comprising:

providing a silicon region disposed above an insulator;

forming dopant diffusion sources in the insulator, wherein the dopant diffusion sources comprise electrical dopants;

forming electrical devices over the dopant diffusion sources; and

subsequently establishing a retrograde doping profile in desired parts of the silicon region by diffusion of the electrical dopants out of the diffusion sources and into the silicon region, wherein diffusion is caused by forming electrical devices.

22. The method of claim 21, wherein forming electrical devices comprises depositing a passivation layer over the silicon region.

23. The method of claim 22, wherein the passivation layer comprises an oxide, borophosphosilicate glass or polysilicon.

24. The method of claim 21, wherein forming dopant diffusion sources comprises implanting electrical dopants substantially adjacent an interface between the insulator and the silicon region.

25. The method of claim 21, wherein forming dopant diffusion sources forms dopant diffusion sources having a dopant concentration of at least about 10²⁰/cm³.

26. The method of claim 21, wherein forming electrical devices comprises forming transistors, wherein source, gate and channel regions of the transistors are formed completely above the dopant diffusion sources.

27. The method of claim 26, further comprising implanting electrical dopants into the gate regions of the transistor devices to adjust threshold voltages of the devices.

28. The method of claim 26, further comprising doping the source and the drain complementarily to the channel region.

29. The method of claim 28, wherein forming electrical devices comprises implanting n-type and p-type dopants into the silicon region to create n-wells and p-wells, respectively.

30. The method of claim 21, wherein the insulator comprises silicon dioxide.

31. The method of claim 30, wherein the insulator is approximately 500 Å

to 2500 Å

thick.

32. A method for integrated circuit fabrication, comprising:

providing a substrate having an electrical device overlying a semiconductor layer, the semiconductor layer overlying an insulating layer;

providing a region comprising electrical dopants in the insulating layer; and

processing the substrate at an elevated temperature to cause diffusion of electrical dopants out of the insulating layer and into the semiconductor layer,

wherein diffusion establishes a retrograde electrical dopant profile in the semiconductor layer.

33. The method of claim 32, wherein processing the substrate comprises forming a passivation layer over the electrical device.

34. The method of claim 32, wherein the electrical device is a transistor.

35. The method of claim 32, wherein the region comprising electrical dopants directly underlies the electrical device.

36. The method of claim 32, further comprising provide a plurality of regions doped with electrical dopant in the insulating layer, wherein some of the regions comprise n-type dopants and other of the regions comprise p-type dopants.

37. The method of claim 32, wherein the semiconductor layer is an epitaxial silicon layer.

38. The method of claim 37, wherein the insulating layer is a buried silicon dioxide layer.

39. The method of claim 32, wherein the substrate is a Separation by IMplanted OXygen (SIMOX) wafer.