Semiconductor devices having regions of induced high and low conductivity, and methods of making the same

• US 7,122,828 B2
• Filed: 09/24/2003
• Issued: 10/17/2006
• Est. Priority Date: 09/24/2003
• Status: Active Grant

• Current Assignee: E. I. du Pont de Nemours and Company (Corteva, Inc.), Lucent Technologies, Inc. (Nokia Corporation)
• Original Assignee: E. I. du Pont de Nemours and Company (Corteva, Inc.), Lucent Technologies, Inc. (Nokia Corporation)
• Inventors: Bao, Zhenan, Katz, Howard Edan, Meth, Jeffrey Scott
• Primary Examiner(s): SMITH, BRADLEY
• Application Number:
  US10/671,303
• Publication Number:
  US 20050062066A1
• Time in Patent Office: 1,119 Days
• Field of Search: 438/99, 257/40
• US Class Current: 257/40
• CPC Class Codes: H10K 10/468 characterised by the gate dielectrics
• CPC Class Codes: H10K 19/10 comprising field-effect transistors
• CPC Class Codes: H10K 85/113 Heteroaromatic compounds comprising sulfur or selene, e.g. polythiophene
• CPC Class Codes: H10K 85/615 Polycyclic condensed aromatic hydrocarbons, e.g. anthracene

Abstract

Semiconductor apparatus comprising: a substrate having a substrate surface; a layer of a first material overlying a first region of the substrate surface; a layer of a semiconductor overlying the layer of first material and overlying a second region of the substrate surface; a first region of the layer of semiconductor, overlying the layer of first material and having a first conductivity; a second region of the layer of semiconductor, overlying the second region of the substrate surface and having a second conductivity; and the first conductivity being substantially different from the second conductivity. Such semiconductor apparatus further comprising a layer of a second material overlying the second region of the substrate surface, the second region of the layer of semiconductor overlying the layer of the second material.

Claims

1. A semiconductor apparatus, comprising:

a substrate having a substrate surface;

a layer of a first material overlying a first region of said substrate surface;

a layer of a first material overlying a second region of said substrate surface;

a layer of a second material overlying a second region of said substrate surface;

a layer of a semiconductor overlying said layer of first material and overlying said layer of second material; and

a first region of said layer of semiconductor overlying said layer of first material and including crystal grains having a first average crystal grain size, a second region of said layer of semiconductor overlying said layer of second material and including crystal grains having a second average crystal grain size, said first average crystal grain size being substantially different from said second average crystal grain size.

2. The semiconductor apparatus of claim 1, in which said first material is a polymer.

3. The semiconductor apparatus of claim 1, in which:

said first region of said layer of semiconductor has a first conductivity;

said second region of said layer of semiconductor has a second conductivity; and

said first conductivity is at least about 100 times as large as said second conductivity.

4. The semiconductor apparatus of claim 1, in which said first average crystal grain size is at least about 10 times as large as said second average crystal grain size.

5. The semiconductor apparatus of claim 1, in which an average separation between crystal grains within said second region of said layer of semiconductor is at least about 10 times as large as an average separation between crystal grains within said first region of said layer of semiconductor.

6. The semiconductor apparatus of claim 1, in which said semiconductor is selected from the group consisting of:

acenes, thiophenes, bithiophenes, phthalocyanines, naphthalene-1,4,5,8-tetracarboxylic diimide compounds, napthalene-1,4,5,8-tetracarboxylic dianhydride, and 11,11,12,12-tetracyanonaphtho-2,6-quinodimethane.

7. The semiconductor apparatus of claim 1, further comprising:

a first gate electrode;

a first source electrode; and

a first drain electrode;

said first source and drain electrodes being in spaced apart conductive contact with a first channel portion of either said first or said second region of said layer of semiconductor, said first gate electrode being positioned to control a conductivity of said first channel portion.

8. The semiconductor apparatus of claim 1, further comprising a layer of a second material overlying said second region of said substrate surface, said second region of said layer of semiconductor overlying said layer of said second material.

9. The semiconductor apparatus of claim 1, in which said layer of first material overlies said second region of said substrate surface.

10. The semiconductor apparatus of claim 2, in which said second material is a polymer.

13. The semiconductor apparatus of claim 1, in which said second material is a polymer.

14. The semiconductor apparatus of claim 3, in which said second material is selected from the group consisting of;

poly(-butyl methacrylate), poly(vinylidene difluoride-co-methyl vinyl ether), polystyrene, poly(p-methoxystyrene), poly(vinylidene difluoride), poly(vinyl acetate), poly(vinyl propionate), poly(methoxy acetate), poly(n-propyl methacrylate), poly(isopropyl methacrylate), poly(n-pentyl methacrylate), poly(vinylidene difluoride-co-ethyl vinyl ether), poly(vinylidene difluoride-co-propyl vinyl ether), poly(dimethylaminoethyl methacrylate), poly(dimethylaminopropyl methacrylate), poly(aminopropyl methacrylate), poly(diethylaminoethyl methacrylate), and blends.

15. The semiconductor apparatus of claim 14, in which said second material comprises poly(n-butyl methacrylate).

16. The semiconductor apparatus of claim 14, in which said second material comprises poly(vinylidine difluoride-co-methyl vinyl ether).

17. The semiconductor apparatus of claim 13, in which said second material comprises charge carrier traps.

18. The semiconductor apparatus of claim 3, in which said first material is selected from the group consisting of:

poly(para-vinyl phenol), poly(4-vinylpyridine), poly(2-vinylnaphthalene), poly(meta-vinyl phenol), poly(ortho-vinyl phenol), poly(para-vinyl phenol)-co-2-hydroxyethylmethacrylate, poly(2-vinylpyridine), poly(2-vinylnaphthalene-co-2-ethylhexyl acrylate, poly(1-vinylnaphthalene), and blends.

19. The semiconductor apparatus of claim 18, in which said first material comprises poly(4-vinylpyridine).

20. The semiconductor apparatus of claim 18, in which said first material comprises poly(2-vinylnaphthalene).

11. The semiconductor apparatus, comprising:

a substrate having a substrate surface;

a layer of a first material overlying a first region of said substrate surface;

a layer of a second material overlying a second region of said substrate surface;

a layer of a semiconductor overlying said layer of first material and overlying said layer of second material; and

a first region of said layer of semiconductor overlying said layer of first material and having a first conductivity, a second region of said layer of semiconductor overlying said layer of second material and having a second conductivity said first conductivity being substantially different from said second conductivity.

12. The semiconductor apparatus of claim 11, in which said layer of first material overlies said second region of said substrate surface.

21. The semiconductor apparatus of claim 11, in which said first material is a polymer.

22. The semiconductor apparatus of claim 11, in which said first conductivity is at least about 100 times as large as said second conductivity.

23. The semiconductor apparatus of claim 11, in which said layer of semiconductor comprises crystal grains, and in which an average crystal grain size within said first region of said layer of semiconductor is at least about 10 times as large as an average crystal grain size within said second region of said layer of semiconductor.

24. A semiconductor apparatus, comprising:

a substrate having a substrate surface;

a layer of a first material overlying a first region of said substrate surface;

a layer of a semiconductor overlying said layer of first material and overlying a second region of said substrate surface;

a first region of said layer of semiconductor, overlying said layer of first material and having a first conductivity, a second region of said layer of semiconductor, overlying said second region of said substrate surface and having a second conductivity, said first conductivity being substantially different from said second conductivity;

first and second gate electrodes;

first and second source electrodes; and

first and second drain electrodes;

said first source and drain electrodes being in spaced apart conductive contact with a first channel portion of either said first region or said second region of said layer of semiconductor, said first gate electrode being positioned to control a conductivity of said first source and first drain electrodes being in spaced apart conductive contact with a first channel portion of either said first region or said second region of said layer of semiconductor, said first gate electrode being positioned to control a conductivity of said first channel portion;

said second source and second drain electrodes being in spaced apart conductive contact with a second channel portion of either said first region or said second region of said layer of semiconductor, said second gate electrode being positioned to control a conductivity of said second channel portion;

wherein said first and second channel portions are mutually isolated by an interposed region of said layer of semiconductor having a substantially lower conductivity than said conductivity of said first and second channel portions.

25. The semiconductor apparatus of claim 24, further comprising a layer of a second material overlying said second region of said substrate surface, said second region of said layer of semiconductor overlying said layer of said second material.

26. The semiconductor apparatus of claim 24, in which said layer of first material overlies said second region of said substrate surface.

27. A semiconductor apparatus, comprising:

a substrate having a substrate surface;

a layer of a first material overlying a first region of said substrate surface;

a layer of a second material overlying a second region of said substrate surface;

a layer of a semiconductor overlying said layer of first material and overlying said layer of second material; and

a first region of said layer of semiconductor overlying said layer of first material and including crystal grains having a first average crystal grain size, a second region of said layer of semiconductor overlying said layer of second material and including crystal grains having a second average crystal grain size, said first average crystal grain size being substantially larger than said second average crystal grain size.

28. The semiconductor apparatus of claim 27, in which said first average crystal grain size is at least about 10 times as large as said second average crystal grain size.

29. The semiconductor apparatus of claim 27, in which an average separation between crystal grains within said second region of said layer of semiconductor is at least about 10 times as large as an average separation between crystal grains within said first region of said layer of semiconductor.

30. The semiconductor apparatus of claim 27, in which:

said first region of said layer of semiconductor has a first conductivity; and

second region of said layer of semiconductor has a second conductivity; and

said first conductivity is at least about 100 times as large as said second conductivity.

31. The semiconductor apparatus of claim 27, further comprising:

a first gate electrode;

a first source electrode; and

a first drain electrode;

said first source and drain electrodes being in spaced apart conductive contact with a first channel portion of either said first region or said second of said layer of semiconductor, said first gate electrode being positioned to control a conductivity of said first channel portion.

32. The semiconductor apparatus of claim 27, in which said layer of first material overlies said second region of said substrate surface.