High-sensitivity optical scanning using memory integration

• US 7,129,509 B2
• Filed: 09/14/2005
• Issued: 10/31/2006
• Est. Priority Date: 06/22/2001
• Status: Expired due to Fees

• Current Assignee: Orbotech Limited (KLA Corporation)
• Original Assignee: Orbotech Limited (KLA Corporation)
• Inventors: Katzir, Yigal, Gur-Arie, Itay, Malinovich, Yacov
• Primary Examiner(s): Allen, Stephone B.
• Assistant Examiner(s): Lee, Patrick J.
• Application Number:
  US11/225,041
• Publication Number:
  US 20060006311A1
• Time in Patent Office: 412 Days
• Field of Search: 250/208.1, 250/559.45, 348/295, 348/319, 348/321, 348125-126, 382/92, 382/584, 382/588, 382/598, 382/88, 382/601, 345/629, 345/634, 345638-640, 345/643
• US Class Current: 250/559.45
• CPC Class Codes: G01N 21/8851 Scan or image signal processing specially adapted therefor, e.g. for scan signal adjustment, for detecting different kinds of defects, for compensating for structures, markings, edges G01N21/8806 and G01N21/93 - G01N21/95692 take precedence; optical measurement of dimensions G01B11/00; optical scanning G02B26/10; image transformation G06T3/00; computerised image enhancement G06T5/00; image processing per se for flaw detection G06T7/0002
• CPC Class Codes: G01N 21/8901 Optical details; Scanning details per se G02B
• CPC Class Codes: G01N 21/956 Inspecting patterns on the surface of objects contactless testing of electronic circuits G01R31/308; testing currency G07D; manufacturing processes per se of semiconductor devices implementing a measuring step H01L22/10
• CPC Class Codes: H01L 27/14645 Colour imagers
• CPC Class Codes: H04N 25/46 by combining or binning pixels
• CPC Class Codes: H04N 25/768 for time delay and integration [TDI]
• CPC Class Codes: H04N 25/772 comprising A/D, V/T, V/F, I/T or I/F converters
• CPC Class Codes: H04N 3/155 Control of the image-sensor operation, e.g. image processing within the image-sensor

Abstract

An inspection system includes a CMOS integrated circuit having integrally formed thereon an at least two dimensional array of photosensors and providing an inspection output representing an object to be inspected. A defect analyzer is operative to receive the inspection output and to provide a defect report.

Claims

1. An inspection system comprising:

an integrated circuit having formed thereon an at least one two dimensional array of photosensors and providing a plurality of pixelized images, each image representing a portion of an object to be inspected;

a composite image generator digitally adding together corresponding pixels of said plurality of images and providing a composite image of said object to be inspected; and

a defect analyzer operative to receive said composite image and to provide a defect report.

2. The inspection system claimed claim 1 and further comprising a scanner having a support assembly supporting said object to be inspected and wherein said integrated circuit is operative to acquire said plurality of images during scanning thereof.

3. The inspection system claimed in claim 1 and wherein said plurality of images comprises a plurality of digital images.

4. The inspection system claimed in claim 1 and wherein each image in said plurality of images at least partially overlaps another image in said plurality of images.

5. The inspection system claimed in claim 4 and wherein an overlap between a first image and a second image comprises at least half of said second image.

6. The inspection system claimed in claim 4 and wherein an overlap between a first image and a second image comprises all of said second image except for a single row of pixels output by said at least one two dimensional array of photosensors.

7. The inspection system claimed in claim 1 and further comprising an illumination assembly generally continuously illuminating said object to be inspected and wherein said integrated circuit is operative to acquire said plurality of images during illumination thereof.

8. The inspection system claimed in claim 1 and further comprising an illumination assembly generally non-continuously illuminating said object to be inspected, and wherein said integrated circuit is operative to acquire said plurality of images during non-continuous illumination thereof.

9. The inspection system claimed in claim 8 and wherein said illumination assembly is operative to provide said non-continuous illumination synchronously with said integrated circuit acquiring images of said object.

10. The inspection system claimed in claim 1 and wherein said integrated circuit has integrally formed thereon, in addition to said at least one two dimensional array of photosensors, at least one A/D converter receiving outputs from said at least one two dimensional array of photosensors.

11. The inspection system claimed in claim 10 and wherein said at least one A/D converter comprises an A/D converter associated with each photosensor in said array.

12. The inspection system claimed in claim 10 and wherein said at least one A/D converter comprises an A/D converter associated with a plurality of photosensors.

13. The inspection system claimed in claim 10 and wherein said CMOS integrated circuit has additionally integrally formed thereon a plurality of digital registers temporarily storing the outputs of said A/D converters.

14. The inspection system claimed in claim 13 and wherein said CMOS integrated circuit has additionally integrally formed thereon:

a digital memory storing image data provided by said array; and

a plurality of digital adders adding the outputs of said digital registers to corresponding image data stored in said digital memory.

15. The inspection system claimed in claim 14 and wherein said digital memory comprises an array of digital memory cells.

16. The inspection system claimed in claim 14 and wherein said CMOS integrated circuit comprises timing circuitry associated with said array, said adders and said digital memory, said timing circuitry generating a sequence of clock cycles.

17. The inspection system claimed in claim 16 and wherein said CMOS integrated circuit comprises:

an input pointer indicating at each clock cycle a location in said digital memory at which to add an output of said at least one A/D converters; and

an output pointer indicating at each clock cycle a location in said digital memory from which to retrieve said image data.

18. The inspection system claimed in claim 17 and wherein said clock is operative to change a location of said input pointer and to change a location of said output pointer at each clock cycle.

19. The inspection system claimed in claim 1 and wherein said integrated circuit is a CMOS integrated circuit.

20. The inspection system claimed in claim 1 and wherein said object is an electrical circuit.

21. A method for inspecting objects comprising:

acquiring a plurality of substantially overlapping pixelized images each image representing a portion of an object to be inspected;

digitally adding together corresponding pixels of said images to provide a composite image of said object; and

analyzing said composite image to detect defects in said object.

22. The method claimed in claim 21 and wherein said acquiring comprises acquiring said images with a CMOS integrated circuit.

23. The method claimed in claim 21 and wherein said acquiring comprises acquiring images of an electrical circuit.

24. The method claimed in claim 21 and wherein said acquiring further comprises illuminating said object using generally continuous illumination.

25. The method claimed in claim 21 and wherein said acquiring further comprises:

acquiring said images at a frame rate; and

illuminating said object using generally non-continuous illumination fluctuating at a intensity fluctuation rate synchronized with said frame rate.

26. The method claimed in claim 21 and wherein said digitally adding comprises converting an image from an analog format to a digital format.

27. The method claimed in claim 26 and wherein said digitally adding comprises:

retrieving a previously acquired image from a memory;

digitally adding a portion of a newly acquired image in a digital format to a portion of said previously acquired image; and

returning to memory an image resulting from said digitally adding a portion.

28. An imaging system comprising:

an integrated circuit having formed thereon an at least one two dimensional array of photosensors and providing a plurality of pixelized images, each image representing a partially overlapping portion of an object to be imaged; and

a composite image generator digitally adding together corresponding pixels of said plurality of images and providing a composite image of said object.

29. The imaging system claimed claim 28 and further comprising a scanner having a support assembly supporting said object to be inspected and wherein said integrated circuit is operative to acquire said plurality of images during scanning thereof.

30. The imaging system claimed in claim 28 and wherein said plurality of images comprises a plurality of digital images.

31. The imaging system claimed in claim 28 and wherein each image in said plurality of images at least partially overlaps another image in said plurality of images.

32. The imaging system claimed in claim 31 and wherein an overlap between a first image and a second image comprises at least half of said second image.

33. The imaging system claimed in claim 31 and wherein an overlap between a first image and a second image comprises all of said second image except for a single row of pixels output by said at least one two dimensional array of photosensors.

34. The imaging system claimed in claim 28 and further comprising an illumination assembly generally continuously illuminating said object to be imaged and wherein said integrated circuit is operative to acquire said plurality of images during illumination thereof.

35. The imaging system claimed in claim 28 and further comprising an illumination assembly generally non-continuously illuminating said object to be imaged, and wherein said integrated circuit is operative to acquire said plurality of images during non-continuous illumination thereof.

36. The imaging system claimed in claim 35 and wherein said illumination assembly is operative to provide said non-continuous illumination synchronously with said integrated circuit acquiring images of said object.

37. The imaging system claimed in claim 28 and wherein said integrated circuit has integrally formed thereon, in addition to said at least two dimensional array of photosensors, at least one A/D converter receiving outputs from said at least one two dimensional array of photosensors.

38. The imaging system claimed in claim 37 and wherein said at least one A/D converter comprises an A/D converter associated with each photosensor in said array.

39. The imaging system claimed in claim 37 and wherein said at least one A/D converter comprises an A/D converter associated with a plurality of photosensors.

40. The imaging system claimed in claim 37 and wherein said integrated circuit has additionally integrally formed thereon a plurality of digital registers temporarily storing the outputs of said A/D converters.

41. The imaging system claimed in claim 40 and wherein said integrated circuit has additionally integrally formed thereon:

a digital memory storing image data provided by said array; and

a plurality of digital adders adding the outputs of said digital registers to corresponding image data stored in said digital memory.

42. The imaging system claimed in claim 41 and wherein said digital memory comprises an array of digital memory cells.

43. The imaging system claimed in claim 41 and wherein said integrated circuit comprises timing circuitry associated with said array, said adders and said digital memory, said timing circuitry generating a sequence of clock cycles.

44. The imaging system claimed in claim 43 and wherein said integrated circuit comprises:

an input pointer indicating at each clock cycle a location in said digital memory at which to add an output of said at least one A/D converters; and

an output pointer indicating at each clock cycle a location in said digital memory from which to retrieve said image data.

45. The imaging system claimed in claim 44 and wherein said clock is operative to change a location of said input pointer and to change a location of said output pointer at each clock cycle.

46. The imaging system claimed in claim 28 and wherein said integrated circuit is a CMOS integrated circuit.

47. The imaging system claimed in claim 28 and wherein said object is an electrical circuit.

48. A method for imaging objects comprising:

acquiring a plurality of substantially overlapping pixelized images each image representing a portion of an object to be imaged; and

digitally adding together corresponding pixels of said images to provide a composite image of said object.

49. The method claimed in claim 48 and wherein said acquiring comprises scanning an at least one two dimensional array of photosensors relative to said object.

50. The method claimed in claim 49 and wherein said acquiring comprises acquiring said images using an at least one two dimensional array of photosensors disposed on a CMOS integrated circuit.

51. The method claimed in claim 48 and wherein said acquiring comprises acquiring said images using an at least one two dimensional array of photosensors disposed on a CMOS integrated circuit.

52. The method claimed in claim 48 and wherein said acquiring comprises acquiring images of an electrical circuit.

53. The method claimed in claim 48 and wherein said acquiring further comprises illuminating said object using generally continuous illumination.

54. The method claimed in claim 48 and wherein said acquiring further comprises:

acquiring said images at a frame rate; and

illuminating said object using generally non-continuous illumination fluctuating at an intensity fluctuation rate synchronized with said frame rate.

55. The method claimed in claim 48 and wherein said digitally adding comprises converting an image from an analog format to a digital format.

56. The method claimed in claim 55 and wherein said digitally adding comprises:

retrieving a previously acquired image from a memory;

digitally adding a portion of a newly acquired image in a digital format to a portion of said previously acquired image; and

returning to memory an image resulting from said digitally adding a portion.