Charge modulation network for multiple power domains for silicon-on-insulator technology

• US 7,129,545 B2
• Filed: 02/24/2005
• Issued: 10/31/2006
• Est. Priority Date: 02/24/2005
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Seitzer, Daryl M., Voldman, Steven H., Gambino, Jeffrey P., Rohrer, Norman J., Cain, David A.
• Primary Examiner(s): Dickey, Thomas L.
• Application Number:
  US10/906,563
• Publication Number:
  US 20060187596A1
• Time in Patent Office: 614 Days
• Field of Search: 257/355, 361/56
• US Class Current: 257/355
• CPC Class Codes: H01L 27/0251 for MOS devices

Abstract

An SOI integrated circuit includes ESD protection on an SOI chip. A first power domain and a second power domain are provided in the SOI chip. In one embodiment, a charge modulation network in the SOI chip between the first power domain and the second power domain mitigates accumulation of electrical charge in an electrically isolated region of the SOI chip. In another embodiment, an ESD protection device in the SOI chip electrically connects the first power domain and the second power domain via a low metal layer to provide a discharge path for accumulated charge.

Claims

1. A silicon-on-insulator (SOI) integrated circuit including electrostatic discharge (ESD) protection comprising:

an SOI chip;

a first power domain in the SOI chip;

a second power domain in the SOI chip;

an ESD protection device in the SOI chip electrically connecting the first power domain and the second power domain via a low metal layer to provide a discharge path for accumulated charge; and

a logic signal line between the first and second power domains and wherein the ESD protection device electrically connects the first power domain and the second power domain at a metal level lower than or equal to the highest metal level on which the logic signal line is routed to provide a discharge path for accumulated charge.

2. The SOI integrated circuit of claim 1 wherein the ESD protection device comprises a diode.

3. The SOI integrated circuit of claim 1 wherein the ESD protection device comprises a plurality of diodes connected in opposite directions between the first power domain and the second power domain.

4. The SOI integrated circuit of claim 1 wherein the ESD protection device comprises a charge modulation network.

5. A method of implementing electrostatic discharge protection in a silicon-on-insulator (SOI) integrated circuit comprising:

defining a plurality of SOI devices in the integrated circuit;

identifying a plurality of power domains in the SOI integrated circuit;

determining if a logic signal traverses more than one of the plurality of power domains;

determining if a circuit path for the logic signal is timing critical; and

connecting a power supply wire for an ESD protection network at a metal level lower than or equal to a highest metal level on which the logic signal is routed if the logic signal traverses more than one power domain and if the circuit path is timing critical.

6. The method of claim 5 wherein connecting a power supply wire for an ESD protection network comprises adding diodes to supplies at a metal level lower than or equal to a highest metal level on which the logic signal is routed.

7. The method of claim 5 further comprising determining if ESD elements are present between supply wires and if so connecting a power supply wire for an ESD protection network comprises connecting ESD elements to supplies at a metal level lower than or equal to a highest metal level on which the logic signal is routed.

8. A method of implementing electrostatic discharge protection in a silicon-on-insulator (SOI) integrated circuit comprising:

defining a plurality of SOI devices in the integrated circuit;

identifying a plurality of power domains in the SOI integrated circuit;

determining if a logic signal traverses more than one of the plurality of power domains;

determining if a circuit path for the logic signal is not timing critical; and

connecting a power supply wire at a metal level higher than a metal level on which a power supply connection for the ESD protection network is routed if the logic signal traverses a single power domain or if the circuit path is not timing critical.