High voltage semiconductor device utilizing a deep trench structure

• US 7,129,559 B2
• Filed: 04/09/2004
• Issued: 10/31/2006
• Est. Priority Date: 04/09/2004
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Hsu, Shun-Liang, Wu, Chen-Bau, Wu, You-Kuo, Jong, Yu-Chang
• Primary Examiner(s): Jackson, Jerome
• Assistant Examiner(s): BUDD, PAUL A
• Application Number:
  US10/821,432
• Publication Number:
  US 20050224896A1
• Time in Patent Office: 935 Days
• Field of Search: 257/499, 257/510, 257/408, 257/511, 257/512
• US Class Current: 257/510
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

A semiconductor device includes a substrate having a source, a drain, and a gate between the source and the drain. Both the source and the drain include a first edge, and the gate includes a first portion. A first deep trench structure is situated under the first portion of the gate and proximate to the first edge of the source and the first edge of the drain.

Claims

1. A semiconductor device comprising:

a substrate including a source and drain, the source having a first edge and the drain having a first edge;

a gate between the source and drain, the gate having a first portion;

a first deep trench structure located directly under the first portion of the gate viewed in a direction from the gate to the substrate, and proximate to the first edge of the source and the first edge of the drain, wherein the first deep trench structure has a depth greater than 0.5 μ

m;

a neighboring semiconductor device; and

a first shallow trench isolation structure located between the semiconductor device and the neighboring semiconductor device.

2. The semiconductor device of claim 1 further comprising:

a second shallow french isolation structure adjacent to the drain wherein the drain is situated between the first shallow trench isolation structure and the second shallow trench isolation structure.

3. The semiconductor device of claim 2 wherein the gate is extended to partially overlay the second shallow trench isolation structure.

4. A semiconductor device comprising:

a substrate including a source and drain, the source having a first edge and the drain having a first edge;

a gate electrode on the substrate and between the source and drain, a first portion of the gate electrode extending past the first edge of the source and the first edge of the drain;

a first deep trench structure located directly under the first portion of the gate electrode viewed in a direction from the gate electrode to the substrate and proximate to the first edge of the source and the first edge of the drain, wherein the first deep trench structure has a depth greater than 0.5 μ

m;

a neighboring semiconductor device; and

a first shallow trench isolation structure located between the semiconductor device and the neighboring semiconductor device.

5. The semiconductor device of claim 4 further comprising:

a second shallow trench isolation structure adjacent to the drain wherein the drain is situated between the first shallow trench isolation structure and the second shallow trench isolation structure.

6. The semiconductor device of claim 5 wherein the gate is extended to partially overlay the second shallow trench isolation structure.

7. A semiconductor device comprising:

a substrate having a source and drain, having widths that are substantially equal and each having a first edge substantially located along a common line on the substrate;

a gate electrode on the substrate and between the source and the drain, the gate electrode having a first portion extending past the first edge of the source and the first edge of the drain;

a first deep trench structure located directly under the first portion of the gate electrode viewed in a direction from the gate electrode to the substrate, the first deep trench structure parallel to the common line on the substrate and proximate to the first edge of the source and the first edge of the drain, wherein the first deep trench structure is substantially deeper than 0.5 μ

m;

a neighboring semiconductor device; and

a first shallow trench isolation structure between the semiconductor device and the neighboring semiconductor device.

8. The semiconductor device of claim 7 further comprising:

a second shallow french isolation structure adjacent to the drain wherein the drain is situated between the first shallow trench isolation structure and the second shallow trench isolation structure.

9. The semiconductor device of claim 8 wherein the gate is extended to partially overlay the second shallow trench isolation structure.