Method of forming a low-K dual damascene interconnect structure
First Claim
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1. A method of forming a low K interconnect structure, comprising:
- providing a film stack comprising a lower low K dielectric layer having a hardened top portion, an upper low K dielectric layer, an etch stop layer and a hard mask;
patterning the hard mask to define a trench;
depositing and patterning a photoresist layer that defines a via within the trench;
etching the via into the upper low K dielectric layer and the hardened top portion of the lower low K dielectric layer;
stripping the photoresist layer; and
etching a trench into the upper low K dielectric layer as defined by the hard mask while simultaneously etching a via into the lower low K dielectric layer using the hardened portion as a mask for the via.
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Abstract
A method of fabricating an interconnect structure comprising etching a via into an upper low K dielectric layer and into a hardened portion of a lower low K dielectric layer. The via is defined by a pattern formed in a photoresist layer. The photoresist layer is then stripped, and a trench that circumscribes the via as defined by a hard mask is etched into the upper low K dielectric layer and, simultaneously, the via that was etched into the hardened portion of the lower low K dielectric layer is further etched into the lower low K dielectric layer. The result is a low K dielectric dual damascene structure.
44 Citations
34 Claims
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1. A method of forming a low K interconnect structure, comprising:
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providing a film stack comprising a lower low K dielectric layer having a hardened top portion, an upper low K dielectric layer, an etch stop layer and a hard mask; patterning the hard mask to define a trench; depositing and patterning a photoresist layer that defines a via within the trench; etching the via into the upper low K dielectric layer and the hardened top portion of the lower low K dielectric layer; stripping the photoresist layer; and etching a trench into the upper low K dielectric layer as defined by the hard mask while simultaneously etching a via into the lower low K dielectric layer using the hardened portion as a mask for the via. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A method of etching a low K material comprising:
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hardening a portion of a low K material; patterning the hardened portion to form at least one opening to low K material that is unhardened; etching the unhardened low K material in the at least one opening to form at least one trench; depositing an antireflective coating layer in the at least one opening and atop the layer until a top surface of the antireflective coating layer is substantially planar; depositing a mask atop the antireflective coating material; and patterning the mask material to define a via, wherein the trench and via form a dual damascene structure. - View Dependent Claims (15, 16, 17, 18, 19)
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20. A method of forming a low K interconnect structure, comprising:
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providing a film stack comprising a lower low K dielectric, an upper low K dielectric layer, and a hard mask; patterning the hard mask to define a trench; depositing and patterning a photoresist layer that defines a via within the trench; etching the via into the upper low K dielectric layer and a portion of the lower low K dielectric layer; stripping the photoresist layer; and etching a trench into the upper low K dielectric layer as defined by the hard mask while simultaneously etching a via into the lower low K dielectric layer. - View Dependent Claims (21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34)
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Specification