Layout technique for C3MOS inductive broadbanding

• US 7,132,727 B2
• Filed: 05/18/2004
• Issued: 11/07/2006
• Est. Priority Date: 05/17/2001
• Status: Expired due to Term

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Green, Michael M., Momtaz, Afshin D.
• Primary Examiner(s): NGUYEN, CUONG QUANG
• Application Number:
  US10/847,832
• Publication Number:
  US 20040207040A1
• Time in Patent Office: 903 Days
• Field of Search: 257528-536
• US Class Current: 257/528
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H03K 19/01707 in asynchronous circuits

Abstract

An improved cell layout for a C3MOS circuit with inductive broadbanding positions the inductor at a distance from the active region to improve isolation and aligns the edges of the resistor, inductor, and transistor regions near the common edge of adjacent cells to decrease the length of the cell-to-cell interconnect lines.

Claims

1. A circuit layout implemented with a semiconductor substrate comprising:

at least one spiral inductor comprising a first edge defined on the semiconductor substrate;

at least one resistor comprising a second edge defined on the semiconductor substrate; and

at least one transistor comprising a third edge defined on the semiconductor substrate;

wherein the first edge, the second edge and the third edge are substantially aligned.

2. The circuit layout of claim 1 wherein the first edge, the second edge and the third edge are substantially aligned with a boundary of a cell defined on the semiconductor substrate.

3. The circuit layout of claim 1 wherein:

the at least one spiral inductor is characterized by a first lateral dimension;

the at least one resistor is characterized by a second lateral dimension;

the at least one transistor is characterized by a third lateral dimension;

the second lateral dimension is substantially smaller than the first lateral dimension; and

the third lateral dimension is substantially smaller than the first lateral dimension.

4. The circuit layout of claim 3 comprising:

at least one first signal line adapted to couple the at least one spiral inductor with the at least one resistor, wherein the at least one first signal line is characterized by a first length; and

at least one second signal line adapted to couple the at least one transistor with the at least one resistor, wherein the at least one second signal line is characterized by a second length and wherein the second length is substantially smaller than the first length.

5. The circuit layout of claim 4 wherein the at least one spiral inductor and the at least one second signal line are positioned on the substrate to isolate the at least one spiral inductor from the at least one second signal line.

6. The circuit layout of claim 4 wherein parasitic capacitance of the at least one first signal line is less than about 20% of a load capacitance associated with the circuit layout.

7. The circuit layout of claim 1 wherein the at least one resistor comprises at least one MOSFET.

8. The circuit layout of claim 1 wherein the at least one resistor comprises at least one polysilicon resistor.

9. The circuit layout of claim 1 wherein the at least one transistor comprises at least one MOSFET.

10. The circuit layout of claim 1 wherein the at least one spiral inductor is coupled to the substrate.

11. A circuit layout disposed on a semiconductor substrate comprising:

a first layout cell comprising;

a first boundary;

a first spiral inductor region comprising a first edge;

a first resistor region comprising a second edge;

a first transistor region comprising a third edge;

wherein the first edge, the second edge and the third edge are aligned substantially adjacent to the first boundary of the first layout cell; and

a second layout cell comprising;

a second boundary that is substantially common with the first boundary of the first layout cell;

a second spiral inductor region comprising a fourth edge;

a second resistor region comprising a fifth edge;

a second transistor region comprising a sixth edge;

wherein the fourth edge, the fifth edge and the sixth edge are aligned substantially adjacent to the second boundary of the second layout cell.

12. The circuit layout of claim 11 wherein

the first spiral inductor region is characterized by a first lateral dimension;

the first resistor region is characterized by a second lateral dimension;

the first transistor region is characterized by a third lateral dimension;

the second spiral inductor region is characterized by the first lateral dimension;

the second resistor region is characterized by the second lateral dimension;

the second transistor region is characterized by the third lateral dimension.

13. The circuit layout of claim 12 wherein:

the first layout cell comprises;

a first set of conductive lines coupling the first spiral inductor region with the first resistor region; and

a second set of conductive lines coupling the first resistor region with the first transistor region, wherein a length characterizing the first set of conductive lines is substantially larger than a length characterizing the second set of conductive lines to isolate the first spiral inductor region from the first transistor region; and

the second layout cell comprises;

a third set of conductive lines coupling the second spiral inductor region with the second resistor region; and

a fourth set of conductive lines coupling the second resistor region with the second transistor region, wherein a length characterizing the third set of conductive lines is substantially larger than a length characterizing the fourth set of conductive lines to isolate the second spiral inductor region from the second transistor region.

14. The circuit layout of claim 13 comprising:

signal interconnect lines coupling the second set of conductive lines in the first layout cell with the second transistor region in the second layout cell;

wherein the alignments of the first edge, the second edge, the third edge, the fourth edge, the fifth edge and the sixth edge facilitate shortening the signal interconnect lines.

15. The circuit layout of claim 13 further comprising:

a load capacitance region coupled to the first set of conductive lines;

wherein the length characterizing the first set of conductive lines results in a parasitic capacitance of less than about 20% of the capacitance of the load capacitance region.

16. The circuit layout of claim 11 wherein:

the first layout cell comprises;

a first set of conductive lines coupling the first spiral inductor region with the first resistor region; and

a second set of conductive lines coupling the first resistor region with the first transistor region, wherein a length characterizing the first set of conductive lines is substantially larger than a length characterizing the second set of conductive lines to isolate the first spiral inductor region from the first transistor region; and

the second layout cell comprises;

a third set of conductive lines coupling the second spiral inductor region with the second resistor region; and

a fourth set of conductive lines coupling the second resistor region with the second transistor region, wherein a length characterizing the third set of conductive lines is substantially larger than a length characterizing the fourth set of conductive lines to isolate the second spiral inductor region from the second transistor region.

17. The circuit layout of claim 16 comprising:

signal interconnect lines coupling the second set of conductive lines in the first layout cell with the second translator region in the second layout cell;

wherein the alignments of the first edge, the second edge, the third edge, the fourth edge, the fifth edge and the sixth edge facilitate shortening the signal interconnect lines.

18. The circuit layout of claim 16 further comprising:

a load capacitance region coupled to the first set of conductive lines;

wherein the length characterizing the first set of conductive lines results in a parasitic capacitance of less than about 20% of the capacitance of the load capacitance region.