Method and system for capturing and bypassing memory transactions in a hub-based memory system

• US 7,133,991 B2
• Filed: 08/20/2003
• Issued: 11/07/2006
• Est. Priority Date: 08/20/2003
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: James, Ralph
• Primary Examiner(s): Elmore, Reba I.
• Application Number:
  US10/645,288
• Publication Number:
  US 20050044304A1
• Time in Patent Office: 1,175 Days
• Field of Search: 711/154, 711/167
• US Class Current: 711/167
• CPC Class Codes: G06F 13/4256 using a clocked protocol
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers

Abstract

A memory hub includes a reception interface that receives data words and captures the data words in response to a first clock signal in a first time domain. The interface also provides groups of the captured data words on an output in response to a second clock signal in a second time domain. A transmission interface is coupled to the reception interface to receive the captured data words and captures the data words in response to a third clock signal in the first time domain. This interface provides the captured data words on an output. Local control circuitry is coupled to the output of the reception interface to receive the groups of data words and develops memory requests corresponding to the groups of data words. The first clock domain is defined by clock signals having frequencies higher than frequencies of clock signals in the second clock domain.

Claims

1. A memory hub, comprising:

a reception interface operable to receive data words and to capture the data words in response to a first clock signal in a first time domain, and operable to provide groups of the captured data words on an output in response to a second clock signal in a second time domain, the second clock signal having a different clock frequency than the first clock signal;

a transmission interface coupled to the reception interface to receive the captured data words and operable to capture the data words in response to a third clock signal in the first time domain, and operable to provide the captured data words on an output; and

local control circuitry coupled to the output of the reception interface to receive the groups of data words, the local control circuitry operable to develop memory requests corresponding to the groups of data words.

2. The memory hub of claim 1 wherein the reception interface comprises:

a first input capture register having an input adapted to receive data words and having a clock input adapted to receive a first reception clock signal, the first input capture register capturing a data word on the input responsive to the first reception clock signal and applying the captured data word on an output;

a second input capture register having an input coupled to the input of the first input capture register and having a clock input adapted to receive a second reception clock signal, the second input capture register capturing a data word on the input responsive to the second reception clock signal and applying the captured data word on an output;

a first storage buffer coupled to the output of the first input capture register and having a clock input adapted to receive a third reception clock signal, the first storage buffer storing sequentially captured data words on the output of the first input capture register;

a second storage buffer coupled to the output of the second input capture register and having a clock input adapted to receive a fourth reception clock signal, the second storage buffer sequentially storing captured data words on the output of the second input capture register;

a first multiplexer coupled to the first storage buffer to receive the stored data words and also coupled to the local control circuitry, the first multiplexer operable in response to selection signals to apply groups of the captured data words to the local control circuitry;

a second multiplexer coupled to the second storage buffer to receive the stored data words and also coupled to the local control circuitry, the second multiplexer operable in response to selection signals to apply groups of the captured data words to the local control circuitry; and

a capture read pointer circuit adapted to receive a fifth clock signal and being coupled to the first and second multiplexers, the capture read pointer operable to apply the selection signals to the multiplexers to supply the groups of captured data words in the buffers to the local control circuitry on a first-in-first-out basis.

3. The memory hub of claim 2 wherein the transmission interface comprises:

a first output capture register having an input coupled to the output of the first input capture register and having a clock input adapted to receive a first transmission clock signal, the first output capture register capturing a data word on the input responsive to the first transmission clock signal and applying the captured data word on an output; and

a second output capture register having an input coupled to the output of the second input capture register and having a clock input adapted to receive a second transmission clock signal, the second output capture register capturing a data word on the input responsive to the second transmission clock signal and applying the captured data word on an output.

4. The memory hub of claim 1 wherein the reception interface further comprises optical interface circuitry adapted to receive optical signals corresponding to the data words and to convert the received optical signals into corresponding electrical signals.

5. The memory hub of claim 4 wherein the transmission interface further comprises optical interface circuitry that converts electrical signals corresponding to the data words into corresponding optical signals.

6. The memory hub of claim 1 wherein the memory hub further comprises:

an upstream reception port adapted to receive and capture upstream data words and operable to provide the captured data words to the local control circuitry; and

an upstream transmission port coupled to the local control circuitry to receive the upstream data words and operable to provide the upstream data words on an output.

7. A memory module, comprising:

a plurality of memory devices; and

a memory hub, comprising;

a reception interface operable to receive data words and to capture the data words in response to a first clock signal in a first time domain, and operable to provide groups of the captured data words on an output in response to a second clock signal in a second time domain, the second clock signal having a different clock frequency than the first clock signal;

a transmission interface coupled to the reception interface to receive the captured data words and operable to capture the data words in response to a third clock signal in the first time domain, and operable to provide the captured data words on an output; and

local control circuitry coupled to the output of the reception interface to receive the groups of data words and also coupled to the memory devices, the local control circuitry operable to apply memory requests corresponding to the groups of data words to the memory devices to access memory cells in at least one of the memory devices responsive to at least some of the memory requests.

8. The memory module of claim 7 wherein the reception interface comprises:

a first input capture register having an input adapted to receive data words and having a clock input adapted to receive a first reception clock signal, the first input capture register capturing a data word on the input responsive to the first reception clock signal and applying the captured data word on an output;

a second input capture register having an input coupled to the input of the first input capture register and having a clock input adapted to receive a second reception clock signal, the second input capture register capturing a data word on the input responsive to the second reception clock signal and applying the captured data word on an output;

a first storage buffer coupled to the output of the first input capture register and having a clock input adapted to receive a third reception clock signal, the first storage buffer storing sequentially captured data words on the output of the first input capture register;

a second storage buffer coupled to the output of the second input capture register and having a clock input adapted to receive a fourth reception clock signal, the second storage buffer sequentially storing captured data words on the output of the second input capture register;

a first multiplexer coupled to the first storage buffer to receive the stored data words and also coupled to the local control circuitry, the first multiplexer operable in response to selection signals to apply groups of the captured data words to the local control circuitry;

a second multiplexer coupled to the second storage buffer to receive the stored data words and also coupled to the local control circuitry, the second multiplexer operable in response to selection signals to apply groups of the captured data words to the local control circuitry; and

a capture read pointer circuit adapted to receive a fifth clock signal and being coupled to the first and second multiplexers, the capture read pointer operable to apply the selection signals to the multiplexers to supply the groups of captured data words in the buffers to the local control circuitry on a first-in-first-out basis.

9. The memory module of claim 8 wherein the transmission interface comprises:

a first output capture register having an input coupled to the output of the first input capture register and having a clock input adapted to receive a first transmission clock signal, the first output capture register capturing a data word on the input responsive to the first transmission clock signal and applying the captured data word on an output; and

a second output capture register having an input coupled to the output of the second input capture register and having a clock input adapted to receive a second transmission clock signal, the second output capture register capturing a data word on the input responsive to the second transmission clock signal and applying the captured data word on an output.

10. The memory module of claim 7 wherein the plurality of memory devices comprise SDRAMs.

11. The memory module of claim 7 wherein the memory hub further comprises:

an upstream reception port adapted to receive and capture upstream data words and operable to provide the captured data words to the local control circuitry; and

an upstream transmission port coupled to the local control circuitry to receive the upstream data words and operable to provide the upstream data words on an output.

12. The memory module of claim 7 wherein the reception interface further comprises optical interface circuitry adapted to receive optical signals corresponding to the data words and to convert the received optical signals into corresponding electrical signals.

13. The memory module of claim 12 wherein the transmission interface further comprises optical interface circuitry that converts electrical signals corresponding to the data words into corresponding optical signals.

14. A memory module, comprising:

a plurality of memory devices; and

a memory hub, comprising;

a physical reception port adapted to receive data words;

wherein the physical reception port comprises;

a first input capture register having an input adapted to receive the data words, an output, and a clock input;

a second input capture register having an input coupled to the input of the first input capture register, an output, and a clocking input;

a first storage buffer coupled to the output of the first input capture register and having a clock input;

a second storage buffer coupled to the output of the second input capture register and having a clock input;

a first multiplexer coupled to the first storage buffer and coupled to the local control circuitry, and having selection inputs;

a second multiplexer coupled to the second storage buffer and coupled to the local control circuitry, and having selection inputs, and

a capture read pointer circuit coupled to the selection inputs of the first and second multiplexers;

a bypass path coupled to the physical reception port;

a physical transmission port coupled to the bypass path; and

local control circuitry coupled to the physical reception port and to the plurality of memory devices.

15. The memory module of claim 14 wherein the physical transmission port comprises:

a first capture register having an input coupled to the bypass path, an output, and a clock input; and

a second capture register having an input coupled to the bypass path, an output, and a clock input.

16. The memory module of claim 14 wherein the bypass path comprises a plurality of conductive lines coupled between the physical reception and transmission ports.

17. The memory module of claim 14 wherein the memory hub further comprises an upstream transmission port and an upstream reception port coupled to the local control circuitry.

18. A memory system, comprising:

a system controller;

a plurality of memory modules, each memory module being coupled to adjacent memory modules through respective high-speed communications links, at least one of the memory modules being coupled to the system controller through a respective high-speed communications link, and each memory module comprising;

a plurality of memory devices;

a reception interface operable to receive data words from the corresponding high-speed communications link and to capture the data words in response to a first clock signal in a first time domain, and operable to provide groups of the captured data words on an output in response to a second clock signal in a second time domain, the second clock signal having a different clock frequency than the first clock signal;

a transmission interface coupled to the reception interface to receive the captured data words and operable to capture the data words in response to a third clock signal in the first time domain, and operable to provide the captured data words on the corresponding high-speed communications link; and

local control circuitry coupled to the output of the reception interface to receive the groups of data words and also coupled to the memory devices, the local control circuitry operable to apply memory requests corresponding to the groups of data words to the memory devices to access memory cells in at least one of the memory devices responsive to at least some of the memory requests.

19. The memory system of claim 18 wherein each of the high-speed communications links comprises an optical communications link.

20. The memory system of claim 18 wherein the reception interface comprises:

a first input capture register having an input adapted to receive data words and having a clock input adapted to receive a first reception clock signal, the first input capture register capturing a data word on the input responsive to the first reception clock signal and applying the captured data word on an output;

a second input capture register having an input coupled to the input of the first input capture register and having a clock input adapted to receive a second reception clock signal, the second input capture register capturing a data word on the input responsive to the second reception clock signal and applying the captured data word on an output;

a first storage buffer coupled to the output of the first input capture register and having a clock input adapted to receive a third reception clock signal, the first storage buffer storing sequentially captured data words on the output of the first input capture register;

a second storage buffer coupled to the output of the second input capture register and having a clock input adapted to receive a fourth reception clock signal, the second storage buffer sequentially storing captured data words on the output of the second input capture register;

a first multiplexer coupled to the first storage buffer to receive the stored data words and also coupled to the local control circuitry, the first multiplexer operable in response to selection signals to apply groups of the captured data words to the local control circuitry;

a second multiplexer coupled to the second storage buffer to receive the stored data words and also coupled to the local control circuitry, the second multiplexer operable in response to selection signals to apply groups of the captured data words to the local control circuitry; and

a capture read pointer circuit adapted to receive a fifth clock signal and being coupled to the first and second multiplexers, the capture read pointer operable to apply the selection signals to the multiplexers to supply the groups of captured data words in the buffers to the local control circuitry on a first-in-first-out basis.

21. The memory system of claim 20 wherein the transmission interface comprises:

a first output capture register having an input coupled to the output of the first input capture register and having a clock input adapted to receive a first transmission clock signal, the first output capture register capturing a data word on the input responsive to the first transmission clock signal and applying the captured data word on an output; and

a second output capture register having an input coupled to the output of the second input capture register and having a clock input adapted to receive a second transmission clock signal, the second output capture register capturing a data word on the input responsive to the second transmission clock signal and applying the captured data word on an output.

22. The memory system of claim 18 wherein the plurality of memory devices comprise SDRAMs.

23. The memory system of claim 18 wherein the memory hub further comprises:

an upstream reception port adapted to receive and capture upstream data words and operable to provide the captured data words to the local control circuitry; and

an upstream transmission port coupled to the local control circuitry to receive the upstream data words and operable to provide the upstream data words on an output.

24. The memory system of claim 18 wherein the reception interface further comprises optical interface circuitry adapted to receive optical signals corresponding to the data words and to convert the received optical signals into corresponding electrical signals.

25. The memory system of claim 24 wherein the transmission interface further comprises optical interface circuitry that converts electrical signals corresponding to the data words into corresponding optical signals.

26. The memory system of claim 18 wherein the plurality of memory modules are coupled in a daisy-chain configuration with a first one of these memory modules being coupled to the system controller through the corresponding high-speed communications link.

27. A computer system, comprising:

a central processing unit (“

CPU”

);

a system controller coupled to the CPU, the system controller having an input port and an output port;

an input device coupled to the CPU through the system controller;

an output device coupled to the CPU through the system controller;

a storage device coupled to the CPU through the system controller;

a plurality of memory modules, each memory module being coupled to adjacent memory modules through respective high-speed communications links, at least one of the memory modules being coupled to the system controller through a respective high-speed communications link, and each memory module comprising;

a plurality of memory devices;

a reception interface operable to receive data words from the corresponding high-speed communications link and to capture the data words in response to a first clock signal in a first time domain, and operable to provide groups of the captured data words on an output in response to a second clock signal in a second time domain, the second clock signal having a different clock frequency than the first clock signal;

a transmission interface coupled to the reception interface to receive the captured data words and operable to capture the data words in response to a third clock signal in the first time domain, and operable to provide the captured data words on the corresponding high-speed communications link; and

local control circuitry coupled to the output of the reception interface to receive the groups of data words and also coupled to the memory devices, the local control circuitry operable to apply memory requests corresponding to the groups of data words to the memory devices to access memory cells in at least one of the memory devices responsive to at least some of the memory requests.

28. The computer system of claim 27 wherein each of the high-speed communications links comprises an optical communications link.

29. The computer system of claim 27 wherein the reception interface comprises:

a first input capture register having an input adapted to receive data words and having a clock input adapted to receive a first reception clock signal, the first input capture register capturing a data word on the input responsive to the first reception clock signal and applying the captured data word on an output;

a second input capture register having an input coupled to the input of the first input capture register and having a clock input adapted to receive a second reception clock signal, the second input capture register capturing a data word on the input responsive to the second reception clock signal and applying the captured data word on an output;

a first storage buffer coupled to the output of the first input capture register and having a clock input adapted to receive a third reception clock signal, the first storage buffer storing sequentially captured data words on the output of the first input capture register;

a second storage buffer coupled to the output of the second input capture register and having a clock input adapted to receive a fourth reception clock signal, the second storage buffer sequentially storing captured data words on the output of the second input capture register;

a first multiplexer coupled to the first storage buffer to receive the stored data words and also coupled to the local control circuitry, the first multiplexer operable in response to selection signals to apply groups of the captured data words to the local control circuitry;

a second multiplexer coupled to the second storage buffer to receive the stored data words and also coupled to the local control circuitry, the second multiplexer operable in response to selection signals to apply groups of the captured data words to the local control circuitry; and

a capture read pointer circuit adapted to receive a fifth clock signal and being coupled to the first and second multiplexers, the capture read pointer operable to apply the selection signals to the multiplexers to supply the groups of captured data words in the buffers to the local control circuitry on a first-in-first-out basis.

30. The computer system of claim 29 wherein the transmission interface comprises:

a first output capture register having an input coupled to the output of the first input capture register and having a clock input adapted to receive a first transmission clock signal, the first output capture register capturing a data word on the input responsive to the first transmission clock signal and applying the captured data word on an output; and

a second output capture register having an input coupled to the output of the second input capture register and having a clock input adapted to receive a second transmission clock signal, the second output capture register capturing a data word on the input responsive to the second transmission clock signal and applying the captured data word on an output.

31. The computer system of claim 27 wherein the plurality of memory devices comprise SDRAMs.

32. The computer system of claim 27 wherein the memory hub further comprises:

an upstream reception port adapted to receive and capture upstream data words and operable to provide the captured data words to the local control circuitry; and

an upstream transmission port coupled to the local control circuitry to receive the upstream data words and operable to provide the upstream data words on an output.

33. The computer system of claim 27 wherein the reception interface further comprises optical interface circuitry adapted to receive optical signals corresponding to the data words and to convert the received optical signals into corresponding electrical signals.

34. The computer system of claim 33 wherein the transmission interface further comprises optical interface circuitry that converts electrical signals corresponding to the data words into corresponding optical signals.

35. The computer system of claim 27 wherein the plurality of memory modules are coupled in a daisy-chain configuration with a first one of these memory modules being coupled to the system controller through the corresponding high-speed communications link.

36. A method of processing downstream memory requests in a memory system including a plurality of memory hubs connected in a serial configuration, the method comprising:

receiving a data word at each memory hub;

latching each received data word in the memory hub responsive to a first clock signal in a first clock domain;

forwarding each latched data word to the next downstream memory hub responsive to a second clock signal in the first time domain; and

processing in each memory hub the latched data word responsive to a third clock signal in a second time domain, the second clock domain being defined by clock signals having rates lower than rates of clock signals in the first time domain.

37. The method of claim 36 wherein a plurality of data words comprises a memory request.

38. The method of claim 37 wherein the memory request comprises a read command.

39. The method of claim 36 wherein the second clock signal comprises a delayed version of the first clock signal.

40. The method of claim 36 wherein the clock signals in the first time domain have rates four times the rate of the third clock signal in the second time domain.

41. The method of claim 36 wherein the serial configuration comprises a plurality of memory hubs coupled in a daisy-chain configuration.