Voltage mode transceiver having programmable voltage swing and external reference-based calibration

• US 7,135,884 B1
• Filed: 01/13/2005
• Issued: 11/14/2006
• Est. Priority Date: 01/13/2005
• Status: Active Grant

• Current Assignee: MediaTek, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Scheffer, Matthew, Talbot, Gerald Robert, Hypher, Austen John
• Primary Examiner(s): Tran, Anh Q.
• Application Number:
  US11/033,757
• Time in Patent Office: 670 Days
• Field of Search: 326 30- 34, 326/86, 326/87, 327108-112
• US Class Current: 326/30
• CPC Class Codes: H03K 17/164 using parallel switching arrangements
• CPC Class Codes: H03K 19/0005 Modifications of input or output impedance
• CPC Class Codes: H04L 25/0278 Arrangements for impedance matching
• CPC Class Codes: H04L 25/028 Arrangements specific to the transmitter end

Abstract

An integrated device includes a voltage mode transmit driver for matching an output impedance to an output transmission line based on a binary code, an input termination module configured for matching an input impedance to an input transmission line based on an input impedance calibration value using thermometer-based decoding. The voltage mode transmit driver includes, for each differential output signal, a resistor network circuit having pull-up circuits and pull-down circuits for changing the voltage on the differential output signal, and having binary weighted resistance values relative to each other. The input termination module includes pull-up circuits and pull-down circuits having inverse hyperbolic resistance values relative to each other, and using thermometer-based decoding to ensure a linear change in input impedance during transitions in the input impedance calibration value. A calibration circuit generates the binary code and the input impedance calibration value based on replicas of the pull-up and pull-down circuits.

Claims

1. An integrated circuit comprising:

a voltage mode transmit driver comprising;

(1) first and second resistor network circuits configured for outputting respective first and second differential signals via respective first and second signal nodes onto first and second differential signal transmission lines having a transmission line impedance, the first and second resistor network circuits each comprising;

(1)(a) pull-up circuits configured for selectively changing an impedance on the corresponding signal node of the corresponding resistor network circuit based on respective pull-up gate signals, the pull-up circuits having respective binary weighted resistance values relative to each other,

(1)(b) pull-down circuits configured for selectively changing an impedance on the corresponding signal node of the corresponding resistor network circuit based on respective pull-down gate signals, the pull-down circuits having the respective binary weighted resistance values relative to each other, and

(2) a driver controller configured for controlling each of the pull-up gate signals and the pull-down gate signals based on a data input signal, a clock signal, and a binary code representing an output impedance correction factor, the driver controller configured for causing the first and second resistor network circuits to match an output impedance of the first and second nodes to the transmission line impedance based on the binary code; and

a calibration circuit having a replica of the pull-up circuits and a replica of the pull-down circuits, the calibration circuit configured for determining the binary code, at prescribed intervals for calibration of the binary weighted resistance values, based on comparing a first voltage to a second voltage across a range of the binary code, the first and second voltages generated by respective first and second potential dividers formed between first and second external precision resistors and the replicas of the pull-up circuits and the pull-down circuits, respectively, the first and second external precision resistors each having a precision resistance representing an ideal transmission line impedance.

2. The integrated circuit of claim 1, further comprising an input termination module comprising a third resistor network circuit configured for receiving third and fourth differential signals, via respective third and fourth signal nodes, from respective third and fourth differential signal transmission lines having a second transmission line impedance, the third resistor network including:

second pull-up circuits each having a first terminal end coupled to the third signal node and a second terminal end coupled to a common node capacitively coupled to ground, the second pull-up circuits configured for selectively changing an impedance on the third signal node based on respective gate signals,

second pull-down circuits, each having a third terminal end coupled to the fourth signal node, a fourth terminal end coupled to a common node, and sharing the gate signal with a corresponding one of the second pull-up circuits, the second pull-down circuits configured for selectively changing an impedance on the fourth signal node based on the respective gate signals, the second pull-down circuits having the inverse hyperbolically weighted resistance values relative to each other;

wherein the calibration circuit further includes a replica of the third resistor network circuit and is configured for generating an input impedance calibration value based on comparing the replica of the third resistor network circuit to the first and second external precision resistors;

wherein the input impedance calibration value corresponds to the gate signals in a prescribed sequence.

3. The integrated circuit of claim 2, wherein the calibration circuit is configured for generating the input impedance calibration value based on comparing third and fourth voltages across a range of the input impedance calibration value, the third and fourth voltages generated based on a third potential divider formed by coupling the first terminal end and the third terminal end of the replica of the third resistor network circuit to the first and second external precision resistors, respectively.

4. The integrated circuit of claim 3, wherein the second pull-up circuits and the second pull-down circuits have respective inverse hyperbolically weighted resistance values relative to each other, the input impedance calibration value having a first contiguous group of bits having a true value, wherein any bits within the input impedance calibration value having a false value are contiguous and separated by the first contiguous group by a single transition.

5. The integrated circuit of claim 4, wherein each pull-up circuit of the voltage mode transmit driver includes a transistor configured for selectively disabling current from passing through the corresponding resistor in response to the corresponding pull-up gate signal, the corresponding resistor coupled to the corresponding signal node of the corresponding resistor network circuit.

6. The integrated circuit of claim 4, wherein the calibration circuit is configured for determining the input impedance calibration value based on successively changing a calibration test value supplied to the replica of the third resistor network as the respective gate signals, and identifying a transition between the third and fourth voltages relative to the change in the calibration test value.

7. The integrated circuit of claim 4, further comprising a plurality of the voltage mode transmit drivers and input termination modules disposed within a contiguous area of the integrated circuit, the voltage mode transmit drivers within the contiguous area each receiving the binary code from said calibration circuit, the input termination modules within the contiguous area each receiving the input impedance calibration value from said calibration circuit.

8. The integrated circuit of claim 2, wherein the driver controller is configured for outputting the pull-up gate signals and the pull-down gate signals of the first resistor network circuit as respective logical complements of the pull-up gate signals and the pull-down gate signals of the second resistor network circuit.

9. The integrated circuit of claim 1, wherein the calibration circuit is configured for determining the binary code based on successively changing a calibration test value supplied to each of the replicas of the pull-up circuits and pull-down circuits as each of the respective pull-up gate signals and pull-down gate signals, and identifying a transition between the first and second voltages relative to the change in the calibration test value.

10. The integrated circuit of claim 1, wherein each pull-up circuit of the voltage mode transmit driver includes a transistor configured for selectively disabling current from passing through the corresponding resistor in response to the corresponding pull-up gate signal, the corresponding resistor coupled to the corresponding signal node of the corresponding resistor network circuit.

17. The method of claim 4, further comprising a plurality of the voltage mode transmit drivers and input termination modules disposed within a contiguous area of the integrated circuit, the voltage mode transmit drivers within the contiguous area each receiving the binary code from said calibration circuit, the input termination modules within the contiguous area each receiving the input impedance calibration value from said calibration circuit.

11. A method in an integrated circuit, the method comprising:

providing in the integrated circuit a voltage mode transmit driver, the voltage mode transmit driver comprising;

(1) first and second resistor network circuits configured for outputting respective first and second differential signals via respective first and second signal nodes onto first and second differential signal transmission lines having a transmission line impedance, the first and second resistor network circuits each comprising;

(1)(a) pull-up circuits configured for selectively changing an impedance on the corresponding signal node of the corresponding resistor network circuit based on respective pull-up gate signals, the pull-up circuits having respective binary weighted resistance values relative to each other,

(1)(b) pull-down circuits configured for selectively changing an impedance on the corresponding signal node of the corresponding resistor network circuit based on respective pull-down gate signals, the pull-down circuits having the respective binary weighted resistance values relative to each other, and

(2) a driver controller configured for controlling each of the pull-up gate signals and the pull-down gate signals based on a data input signal, a clock signal, and a binary code representing an output impedance correction factor;

causing, by the driver controller, the first and second resistor network circuits to match an output impedance of the first and second nodes to the transmission line impedance based on the binary code; and

determining the binary code at prescribed intervals for calibration of the binary weighted resistance values by a calibration circuit having a replica of the pull-up circuits and a replica of the pull-down circuits, the calibration circuit configured for determining the binary code based on comparing a first voltage to a second voltage across a range of the binary code, the first and second voltages generated by respective first and second potential dividers formed between first and second external precision resistors and the replicas of the pull-up circuits and the pull-down circuits, respectively, the first and second external precision resistors each having a precision resistance representing an ideal transmission line impedance.

12. The method of claim 11, further comprising providing an input termination module comprising a third resistor network circuit configured for receiving third and fourth differential signals, via respective third and fourth signal nodes, from respective third and fourth differential signal transmission lines having a second transmission line impedance, the third resistor network including:

second pull-up circuits each having a first terminal end coupled to the third signal node and a second terminal end coupled to a common node capacitively coupled to ground, the second pull-up circuits configured for selectively changing an impedance on the third signal node based on respective gate signals,

second pull-down circuits, each having a third terminal end coupled to the fourth signal node, a fourth terminal end coupled to a common node, and sharing the gate signal with a corresponding one of the second pull-up circuits, the second pull-down circuits configured for selectively changing an impedance on the fourth signal node based on the respective gate signals, the second pull-down circuits having the inverse hyperbolically weighted resistance values relative to each other;

wherein the calibration circuit further includes a replica of the third resistor network circuit and is configured for generating an input impedance calibration value based on comparing the replica of the third resistor network circuit to the first and second external precision resistors;

wherein the input impedance calibration value corresponds to the gate signals in a prescribed sequence.

13. The method of claim 12, wherein the input impedance calibration value is generated based on the calibration circuit comparing third and fourth voltages across a range of the input impedance calibration value, the third and fourth voltages generated based on a third potential divider formed by coupling the first terminal end and the third terminal end of the replica of the third resistor network circuit to the first and second external precision resistors, respectively.

14. The method of claim 13, wherein the second pull-up circuits and the second pull-down circuits have respective inverse hyperbolically weighted resistance values relative to each other, the input impedance calibration value having a first contiguous group of bits having a true value, wherein any bits within the input impedance calibration value having a false value are contiguous and separated by the first contiguous group by a single transition.

15. The method of claim 14, wherein each pull-up circuit of the voltage mode transmit driver includes a transistor configured for selectively disabling current from passing through the corresponding resistor in response to the corresponding pull-up gate signal, the corresponding resistor coupled to the corresponding signal node of the corresponding resistor network circuit.

16. The method of claim 14, wherein the calibration circuit is configured for determining the input impedance calibration value based on successively changing a calibration test value supplied to the replica of the third resistor network as the respective gate signals, and identifying a transition between the third and fourth voltages relative to the change in the calibration test value.

18. The method of claim 12, wherein the driver controller is configured for outputting the pull-up gate signals and the pull-down gate signals of the first resistor network circuit as respective logical complements of the pull-up gate signals and the pull-down gate signals of the second resistor network circuit.

19. The method of claim 11, wherein the calibration circuit is configured for determining the binary code based on successively changing a calibration test value supplied to each of the replicas of the pull-up circuits and pull-down circuits as each of the respective pull-up gate signals and pull-down gate signals, and identifying a transition between the first and second voltages relative to the change in the calibration test value.

20. The method of claim 11, wherein each pull-up circuit of the voltage mode transmit driver includes a transistor configured for selectively disabling current from passing through the corresponding resistor in response to the corresponding pull-up gate signal, the corresponding resistor coupled to the corresponding signal node of the corresponding resistor network circuit.

21. A method in an integrated circuit, the method comprising:

supplying a voltage signal to a first input of a comparator in the integrated circuit;

providing in the integrated circuit a digital to analog converter configured for outputting a reference signal to a second input of the comparator in response to a digital reference value;

determining a first voltage value based on setting the digital reference value to a minimum value, and successively incrementing the digital reference value until detecting a first transition in the comparator, the first voltage value corresponding to the digital reference value upon detection of the first transition;

determining a second voltage value based on setting the digital reference value to a maximum value, and successively decrementing the digital reference value until detecting a second transition in the comparator, the second voltage value corresponding to the digital reference value upon detection of the second transition; and

determining the voltage value of the voltage signal based on averaging the first voltage value and the second voltage value.