Universal single-ended parallel bus
First Claim
Patent Images
1. A receiver, comprising:
- a first buffer that is operable to receive a first signal and to process the first signal thereby generating a reference signal, wherein the first signal is a differential signal; and
a second buffer that is operable to receive a second signal and to compare a level of the second signal to the reference signal to determine a logic level of the second signal.
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Abstract
A high speed data communication system uses a single-ended bus architecture with a reference signal extracted from a differential periodic signal that is transmitted along with single-ended data. By using a periodic signal such a clock signal with approximately 50% duty cycle, a much more stable and accurate reference signal is established for receiving single-ended data.
107 Citations
20 Claims
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1. A receiver, comprising:
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a first buffer that is operable to receive a first signal and to process the first signal thereby generating a reference signal, wherein the first signal is a differential signal; and a second buffer that is operable to receive a second signal and to compare a level of the second signal to the reference signal to determine a logic level of the second signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A communication system, comprising:
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a transmitter that is operable to transmit a first signal and a second signal, wherein the first signal is a differential signal; a receiver that includes a first buffer and a second buffer; wherein the transmitter and the receiver are communicatively coupled via a bus; wherein the first buffer is operable to receive the first signal from the bus and to process the first signal thereby generating a reference signal; and wherein the second buffer is operable to receive the second signal from the bus and to compare a level of the second signal to the reference signal to determine a logic level of the second signal. - View Dependent Claims (12, 13, 14, 15, 16)
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17. An integrated circuit, comprising:
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a first functional block that is operable to receive a first signal and to process the first signal thereby generating a second signal, wherein the first signal is a differential signal; a second functional block that is operable to receive a third signal and to process the third signal thereby generating a fourth signal; and wherein the second functional block is operable to compare the fourth signal and the second signal to determine bit values within the third signal. - View Dependent Claims (18, 19, 20)
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Specification