Control and supervisory signal transmission system for changing a duty factor of a control signal
First Claim
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1. A control and supervisory signal transmission system comprising:
- a controller;
a plurality of controlled devices, each of the controlled device having a controlled section and a sensor section for monitoring the controlled section;
a parent station connected to the controller and a data signal line common to the plurality of controlled devices; and
a plurality of child stations associated with the plurality of controlled devices and connected to the data signal line and the associated controlled devices,wherein a control signal from the controller is transmitted to the controlled section and a supervisory signal from the sensor section is transmitted to the controller through a data signal line,wherein the parent station further comprises;
timing generating means for generating a predetermined timing signal that synchronizes with a clock having a predetermined cycle;
a parent station output section that changes a duty factor between a period in which the control data signal is at a non-power-supply-voltage level that is lower than a power supply voltage and higher than high-level signals in other circuit portions and a subsequent period in which the control signal is at the power supply voltage in accordance with each data value in the control signal inputted from the controller in each cycle of the clock under the control of the timing signal to convert the control data signal into a serial pulse voltage signal and output the serial pulse voltage signal onto the data signal line; and
a parent station input section for detecting a supervisory data signal superimposed on the serial pulse voltage signal transmitted through the data signal line in each cycle of the clock under the control of the timing signal to extract each data value from the serial supervisory signal, convert the extracted signal into the supervisory signal, and input the supervisory signal into the controller, andwherein each of the plurality of child stations further comprises;
a child station output section for identifying the duty factor between a period in which the control signal is at a level different from the power supply voltage of the serial pulse voltage signal and a subsequent period in which the control signal is at the power-supply voltage level in each cycle of the clock under the control of the timing signal to extract value values from the control data signal and provide data in the data values that is relevant to the child station to the controlled section; and
a child station input section for producing a supervisory data signal in accordance with the value in the associated sensor section under the control of the timing signal and superimposing the supervisory data signal at a predetermined position of the serial pulse voltage signal.
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Abstract
A parent station output section changes a duty factor between a period in which a control data signal is at a level (high-potential low-level) lower than a power supply voltage Vx but higher than high-level signal in other circuit portions and a subsequent period in which the control data signal is at the power supply voltage Vx level to convert the control data signal into a serial pulse voltage signal and output the voltage signal onto data signal lines D+ and D− in accordance with each data value in the control data signal inputted from a controller in each cycle of a clock.
17 Citations
11 Claims
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1. A control and supervisory signal transmission system comprising:
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a controller; a plurality of controlled devices, each of the controlled device having a controlled section and a sensor section for monitoring the controlled section; a parent station connected to the controller and a data signal line common to the plurality of controlled devices; and a plurality of child stations associated with the plurality of controlled devices and connected to the data signal line and the associated controlled devices, wherein a control signal from the controller is transmitted to the controlled section and a supervisory signal from the sensor section is transmitted to the controller through a data signal line, wherein the parent station further comprises; timing generating means for generating a predetermined timing signal that synchronizes with a clock having a predetermined cycle; a parent station output section that changes a duty factor between a period in which the control data signal is at a non-power-supply-voltage level that is lower than a power supply voltage and higher than high-level signals in other circuit portions and a subsequent period in which the control signal is at the power supply voltage in accordance with each data value in the control signal inputted from the controller in each cycle of the clock under the control of the timing signal to convert the control data signal into a serial pulse voltage signal and output the serial pulse voltage signal onto the data signal line; and a parent station input section for detecting a supervisory data signal superimposed on the serial pulse voltage signal transmitted through the data signal line in each cycle of the clock under the control of the timing signal to extract each data value from the serial supervisory signal, convert the extracted signal into the supervisory signal, and input the supervisory signal into the controller, and wherein each of the plurality of child stations further comprises; a child station output section for identifying the duty factor between a period in which the control signal is at a level different from the power supply voltage of the serial pulse voltage signal and a subsequent period in which the control signal is at the power-supply voltage level in each cycle of the clock under the control of the timing signal to extract value values from the control data signal and provide data in the data values that is relevant to the child station to the controlled section; and a child station input section for producing a supervisory data signal in accordance with the value in the associated sensor section under the control of the timing signal and superimposing the supervisory data signal at a predetermined position of the serial pulse voltage signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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Specification
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Current AssigneeAnywire Corp. (Mitsubishi Electric Corporation)
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Original AssigneeAnywire Corp. (Mitsubishi Electric Corporation)
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InventorsYukawa, Kouji, Saitou, Yoshitane, Nishikido, Kenji, Mori, Yasushi
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Primary Examiner(s)Rinehart, Mark H.
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Assistant Examiner(s)PHAN, RAYMOND NGAN
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Application NumberUS10/322,573Publication NumberTime in Patent Office1,450 DaysField of Search710105-106, 710305-309, 710/110, 710/313, 710/58, 710/6, 710/61, 707208-209, 707/233, 375/354US Class Current710/306CPC Class CodesG05B 19/042 using digital processors G0...G05B 2219/25028 Power, data and clock busG05B 2219/25132 Superposition data signals ...G05B 2219/25188 Superposition high frequenc...H04B 3/50 Systems for transmission be...
