Active protection circuit for load mismatched power amplifier

• US 7,148,748 B2
• Filed: 07/02/2004
• Issued: 12/12/2006
• Est. Priority Date: 08/09/2002
• Status: Expired due to Term

• Current Assignee: Qorvo US, Inc. (Qorvo, Inc.)
• Original Assignee: TriQuint Semiconductor Incorporated (Qorvo, Inc.)
• Inventors: Apel, Thomas R.
• Primary Examiner(s): Tra, Quan
• Assistant Examiner(s): Luu, An T.
• Application Number:
  US10/884,135
• Publication Number:
  US 20040239428A1
• Time in Patent Office: 893 Days
• Field of Search: 330/259, 330/260, 330/261, 330/270, 330/271, 330/273, 330/284, 330/285, 330/290
• US Class Current: 330/279
• CPC Class Codes: H03F 1/52 Circuit arrangements for protecting such amplifiers monitoring arrangements G01R31/28; increasing reliability in communication systems, e.g. using redundancy H04B1/74
• CPC Class Codes: H03G 3/3042 in modulators, frequency-changers, transmitters or power amplifiers transmission power control in bidirectional transmission systems H04W52/04

Abstract

A peak detector detects an amplifier output overvoltage condition if the amplifier drives a mismatched load impedance. In response to the detected overvoltage condition, a clamping transistor lowers a reference DC bias voltage supplied by a bias circuit to the amplifier. The lowered reference DC bias voltage lowers amplifier gain and output power, thus protecting the amplifier.

Claims

1. A method of protecting an amplifier, comprising the acts of:

providing an amplifier including an input terminal adapted to receive a RF signal, an output terminal adapted to output the RF signal after amplification therein, and at least one amplifier stage between the input and output terminals;

providing a reference DC bias voltage to at least one said amplifier stage of the amplifier;

detecting an overpeak voltage output of the amplifier, wherein said detecting comprises using a series of diodes coupled to the output terminal of the amplifier; and

reducing the reference DC bias voltage in response to the detected overpeak voltage.

2. The method of claim 1, wherein detecting the overpeak voltage comprises using a peak detector diode coupled to a node of the series of diodes.

3. The method of claim 2, wherein reducing the reference DC bias voltage comprising using a clamping transistor that conducts in response to the detected overpeak voltage.

4. The method of claim 3, wherein using a clamping transistor comprises shunting current from an output terminal of a bias transistor outputting the reference DC bias voltage.

5. The method of claim 1, wherein the amplifier includes a plurality of the amplifier stages.

6. The method of claim 5, wherein the reference DC bias voltage is provided to a last of the plurality of amplifier stages.

7. The method of claim 5, wherein the reference DC bias voltage is provided at least to a said amplifier stage other than a last of the amplifier stages.

8. The method of claim 1, wherein there are a plurality of the amplifier stages, each of which is provided with a respective reference DC bias voltage, and the respective reference DC bias voltages provided to at least two of the amplifier stages are reduced in response to the detected overpeak voltage.

9. The method of claim 1, wherein reducing the reference DC bias voltage comprising using a clamping transistor that conducts in response to the detected overpeak voltage.

10. The method of claim 9, wherein the conduction by the clamping transistor shunts current from an output terminal of a bias transistor outputting the reference DC bias voltage.

11. A method of protecting an amplifier, comprising the acts of:

providing an amplifier including an input terminal adapted to receive a RF signal, an output terminal adapted to output the RF signal after amplification therein, and at least one amplifier stage between the input and output terminals;

providing a reference DC bias voltage to at least one said amplifier stage of the amplifier;

detecting an overpeak voltage output of the amplifier at the output terminal wherein detecting the overpeak voltage comprises using a plurality of diodes connected in series with the output terminal of the amplifier; and

reducing the reference DC bias voltage in response to the detected overpeak voltage using a clamping transistor that shunts current from an output terminal of a transistor of a bias circuit coupled to the at least one said amplifier stage.

12. The method of claim 11, wherein the amplifier includes a plurality of the amplifier stages.

13. The method of claim 12, wherein the reference DC bias voltage is provided to a last of the plurality of amplifier stages.

14. The method of claim 12, wherein the reference DC bias voltage is provided at least to a said amplifier stage other than a last of the amplifier stages.

15. The method of claim 11, wherein there are a plurality of the amplifier stages, each of which is provided with a respective reference DC bias voltage, and the respective reference DC bias voltages provided to at least two of the amplifier stages are reduced in response to the detected overpeak voltage.

16. An electronic circuit comprising:

an amplifier including an input terminal adapted to receive a RF signal, an output terminal adapted to output the RF signal after amplification therein, and at least one amplifier stage between the input and output terminals, the at least one amplifier stage receiving a reference DC bias voltage;

a first series of diodes coupled to the output terminal;

a bias transistor comprising an output terminal from which reference DC bias voltage is output; and

a clamping transistor, wherein conduction by the clamping transistor depends on conduction by the first series of diodes, and conduction by the clamping transistor reduces the DC reference voltage output by the bias transistor.

17. The electronic circuit of claim 16, further comprising at least one diode coupled that has an output terminal coupled to the output terminal of the amplifier.

18. The electronic circuit of claim 16, further comprising an emitter follower in series with a node of the first series of diodes and with a control input of the clamping transistor.

19. The electronic circuit of claim 18, further a peak detector diode coupled between the node of the first series of diodes and a control input of the emitter follower.

20. The electronic circuit of claim 16, wherein the amplifier includes a plurality of the amplifier stages, and the reference DC bias voltage is provided to a last of the plurality of amplifier stages.

21. The electronic circuit of claim 16, wherein the amplifier includes a plurality of the amplifier stages, and the reference DC bias voltage is provided at least to a said amplifier stage other than a last of the amplifier stages.

22. The electronic circuit of claim 16, wherein there are a plurality of the amplifier stages, each of which is provided with a respective reference DC bias voltage, and the conduction by the clamping transistor reduces the respective reference DC bias voltages provided to at least two of the amplifier stages.

23. An electronic circuit comprising:

an amplifier including an input terminal adapted to receive a RF signal, an output terminal adapted to output the RF signal after amplification therein, and at least one amplifier stage between the input and output terminals, the at least one amplifier stage receiving a reference DC bias voltage;

a first series of diodes, wherein a first of the diodes has an input terminal coupled to the output terminal of the amplifier, the first series of diodes being operable to conduct in response to an overpeak voltage at the output terminal of the amplifier;

a second series of diodes, wherein a first of the diodes has an input terminal coupled to a ground and a last of the diodes has an output coupled to the output terminal of the amplifier; and

a control circuit coupled to a node of the first series of diodes, and operable to reduce the reference DC voltage in response to conduction by the first series of diodes.

24. The electronic circuit of claim 23, wherein the control circuit includes a clamping transistor that conducts in response to the conduction by the first series of diodes, the conduction of the clamping transistor causing the reduction in the reference DC voltage.

25. The electronic circuit of claim 24, wherein the conduction by the clamping transistor shunts current from an output terminal of a bias transistor that provides the reference DC voltage to the at least one said amplifier stage.

26. An electronic circuit comprising:

an amplifier including an input terminal adapted to receive a RE signal, an output terminal adapted to output the RF signal after amplification therein, and at least one amplifier stage between the input and output terminals, the at least one amplifier stage receiving a reference DC bias voltage;

a bias circuit providing the reference DC bias voltage to the at least one amplifier stage; and

a clamping transistor, wherein conduction by the clamping transistor depends on whether a voltage of the RE signal at the output terminal exceeds an overpeak voltage, and the conduction by the clamping transistor reduces the DC reference voltage provided to the at least one amplifier stage.

27. The electronic circuit of claim 26, further comprising a first series of diodes, wherein a first of the diodes has an input terminal coupled to the output terminal of the amplifier, the first series of diodes being operable to conduct in response to the overpeak voltage, and the conduction by the clamping transistor depends on the conduction by the first series of diodes.