Initializing system memory

• US 7,149,890 B2
• Filed: 11/21/2003
• Issued: 12/12/2006
• Est. Priority Date: 11/21/2003
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Justen, Jordan L.
• Primary Examiner(s): Browne, Lynne H.
• Assistant Examiner(s): Patel, Nitin C.
• Application Number:
  US10/719,801
• Publication Number:
  US 20050114620A1
• Time in Patent Office: 1,117 Days
• Field of Search: 713/1, 713/2, 713/100, 711/100, 711/202, 711/170, 711/206
• US Class Current: 713/2
• CPC Class Codes: G06F 12/08 in hierarchically structured memory systems, e.g. virtual memory systems
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 12/10 Address translation
• CPC Class Codes: G06F 2212/2515 being configurable for different purposes, e.g. as cache or non-cache memory

Abstract

Systems and techniques described herein may include both memory mapped and non-memory mapped firmware. A memory region may be in communication with at least one of the memory mapped non-volatile memory region. The memory region may be a cache memory region, and a paging mechanism may be implemented in at least a portion of the cache memory.

Claims

1. A data processing system comprising:

a memory mapped non-volatile memory region including one or more memory mapped executable instructions to initialize the data processing system;

a non-memory mapped non-volatile memory region, the non-memory mapped non-volatile memory region including one or more non-memory mapped executable instructions to initialize the data processing system; and

a third memory region in communication with at least one of the memory mapped non-volatile memory region and the non-memory mapped non-volatile memory region.

2. The system of claim 1, wherein the memory mapped non-volatile memory region comprises a first integrated circuit including a hardware mechanism to enable access to the one or more executable instructions using a processor memory read.

3. The system of claim 2, wherein the non-memory mapped non-volatile memory region comprises a second integrated circuit separate from the first integrated circuit.

4. The system of claim 3, wherein the second integrated circuit does not include a hardware mechanism to enable access to the one or more non-memory mapped executable instructions using a processor memory read.

5. The system of claim 1, wherein at least one of the memory mapped non-volatile memory region and the non memory-mapped non-volatile memory region is implemented as flash memory.

6. The system of claim 1, wherein the third memory region comprises cache memory.

7. The system of claim 6, further including a microprocessor, and wherein the cache memory is integrated with the microprocessor.

8. The system of claim 6, wherein the cache memory is partitioned to include a first region to store data and a second region to store one or more pages.

9. The system of claim 8, wherein the cache memory is partitioned to further include a third region to store one or more page tables.

10. The data processing system of claim 1, further comprising a paging handler to access the non-memory mapped non-volatile memory region and load the non-memory mapped executable instructions into the memory region.

11. A method of initializing a computer system, comprising:

(a) accessing memory mapped firmware using a processor memory read;

(b) executing an initialization instruction included in the memory mapped firmware;

(c) copying a page including a second initialization instruction from non-memory mapped firmware to a second memory region;

(d) translating an address in the second initialization instruction to a physical address of the copied page in the second memory region; and

(e) executing the second initialization instruction.

12. The method of claim 11, wherein actions (a) through (e) are performed prior to initializing a main memory of the computer system.

13. The method of claim 11, further comprising prior to (c), initializing at least a portion of a cache memory as random access memory.

14. The method of claim 11, further comprising prior to (c):

(b)(1) attempting to access a desired page of data stored in the second memory region;

(b)(2) receiving a page fault signal indicating that the desired page of data is not stored in the second memory region; and

(b)(3) copying the desired page of data from non-memory mapped firmware to the second memory region.

15. The method of claim 14, further comprising receiving a fault serviced signal indicating that the desired of page of data is in the second memory region.

16. The method of claim 15, further comprising executing an instruction included in the desired page of data stored in the second memory region.

17. The method of claim 11, further comprising partitioning the second memory region to include a region for data and a region for pages.

18. The method of claim 17, further comprising partitioning the second memory region to include a region for page tables.

19. A chipset comprising:

a memory mapped non-volatile memory region in including one or more memory mapped executable instructions to initialize the data processing system;

a non-memory mapped non-volatile memory region, the non-memory mapped non-volatile memory region including one or more non-memory mapped executable, instructions to initialize the data processing system; and

a third memory region in communication with at least one of the memory mapped non-volatile memory region and the non-memory mapped non-volatile memory region.

20. The chipset of claim 19, wherein the memory mapped non-volatile memory region comprises a first integrated circuit included in the chipset, the first integrated circuit including a hardware mechanism to enable access to the one or more executable instructions using a processor memory read.

21. The chipset of claim 20, wherein the non-memory mapped non-volatile memory region comprises a second integrated circuit included in the chipset, the second integrated circuit separate from the first integrated circuit.

22. The chipset of claim 21, wherein the second integrated circuit does not include a hardware mechanism to enable access to the one or more non-memory mapped executable instructions using a processor memory read.

23. The chipset of claim 21, wherein at least one of the memory mapped non-volatile memory region and the non memory-mapped non-volatile memory region is implemented as flash memory.

24. The chipset of claim 19, wherein the chipset is in communication with a microprocessor.

25. The chipset of claim 19, wherein the third memory region comprises cache memory.

26. The chipset of claim 25, wherein the cache memory is configurable to be partitioned to include a first region to store data and a second region to store one or more pages.

27. The chipset of claim 26, wherein the cache memory is configurable to be partitioned to further include a third region to store one or more page tables.

28. The chipset of claim 19, further comprising a paging handler to implement a paging mechanism.

29. An article of manufacture comprising a machine accessible medium containing code having instructions that, when executed, cause the machine to:

(a) access memory mapped firmware using a processor memory read;

(b) execute an initialization instruction included in the memory mapped firmware;

(c) copy a page including a second initialization instruction from non-memory mapped firmware to a second memory region;

(d) translating an address in the second initialization instruction to a physical address of the copied page in the second memory region; and

(e) execute the second initialization instruction.

30. The article of claim 29, wherein the instructions on machine accessible medium cause the machine to perform (a) through (e) prior to initializing a main memory of the computer system.

31. The article of claim 29, the instructions on machine accessible medium further causing the machine to initialize at least a portion of a cache memory as random access memory prior to (c).

32. The article of claim 29, the instructions on machine accessible medium further causing the machine to, prior to (c):

(b)(1) attempt to access a desired page of data stored in the second memory region; and

(b)(2) upon receiving a page fault signal indicating that the desired page of data is not stored in the second memory region, copy the desired page of data from non-memory mapped firmware to the second memory region.

33. The article of claim 32, the instructions on machine accessible medium further causing the machine to receive a fault serviced signal indicating that the desired of page of data is in the second memory region.

34. The article of claim 33, the instructions on machine accessible medium further causing the machine to execute a third instruction included in the desired page of data stored in the second memory region.

35. The article of claim 29, wherein the instructions on machine accessible medium cause the machine to partition the second memory region to include a region for data and a region for pages.

36. The article of claim 29, wherein the instructions on machine accessible medium cause the machine to partition the second memory region to include a region for page tables.