Dynamic master/slave configuration for multiple expansion modules

• US 7,152,125 B2
• Filed: 09/25/2001
• Issued: 12/19/2006
• Est. Priority Date: 09/25/2001
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Garney, John I., Royer, Robert J. Jr.
• Primary Examiner(s): Nguyen, Tanh Q.
• Application Number:
  US09/963,184
• Publication Number:
  US 20030061428A1
• Time in Patent Office: 1,911 Days
• Field of Search: 710/2, 710/5, 710/8, 710/10, 710/62, 710/64, 710/72, 710/104, 710/120, 710/110, 710300-306, 710/38, 710/48, 710260-261, 718/100, 712/31, 712/214, 709208-211, 700/3
• US Class Current: 710/300
• CPC Class Codes: G06F 2209/5017 Task decomposition
• CPC Class Codes: G06F 9/5027 the resource being a machine, e.g. CPUs, Servers, Terminals

Abstract

A computing system having expansion modules. One of the expansion modules is identified as a master module. The other modules act as slaves to the master module. The central processing unit routes a task to either the master module for portioning out or to all of the expansion modules. The master module then receives completion signals from all of the active slave modules and then provides only one interrupt to the central processing unit for that task.

Claims

1. A computing system, comprising:

a central processing unit to assign a processing task;

at least two expansion modules, wherein one expansion module is designated as a master module such that any expansion module may be designated as the master module, the master module being the only one master module, and the only one master module is designated based upon the processing task, the only one master module to;

perform a portion of the processing task as assigned to the only one master module;

receive at least one completion signal of at least another portion of the processing task from at least one other module; and

notify the central processing unit only upon reception of all completion signals for the processing task, such that only the only one master module notifies the central processing unit; and

a system expansion bus communicatively coupled to the central processing unit and the expansion modules to allow communication between the central processing unit and the only one master module.

2. The computing system of claim 1, wherein the expansion modules are peripheral component interconnect modules.

3. The computing system of claim 1, wherein the system expansion bus is an ISA bus.

4. The computing system of claim 1, wherein the expansion modules are memory modules.

5. The computing system of claim 4, wherein the memory modules are polymer ferroelectric memory modules.

6. The computing system of claim 1, wherein the central processing unit is operable to designate the only one master module based upon a type of task.

7. The computing system of claim 1, wherein the central processing unit is operable to designate the only one master module dynamically.

8. The computing system of claim 1, wherein the only one master module is predesignated.