Structured integrated circuit device

• US 7,157,937 B2
• Filed: 07/22/2005
• Issued: 01/02/2007
• Est. Priority Date: 07/27/2004
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: eASIC Corporation (Intel Corporation)
• Inventors: Or-Bach, Zvi, Apostol, Adrian, Levinthal, Adam, Zeman, Richard, Iacobut, Romeo, Avram, Petrica, Kapel, Alon, Wurman, Ze', Grigore, George C.
• Primary Examiner(s): Tran; Anh Q.
• Application Number:
  US11/186,923
• Publication Number:
  US 20060028241A1
• Time in Patent Office: 529 Days
• Field of Search: 326 37- 71, 326/101
• US Class Current: 326/41
• CPC Class Codes: G01R 31/3172 Optimisation aspects, e.g. using functional pin as test pin, pin multiplexing
• CPC Class Codes: G01R 31/318516 Test of programmable logic devices [PLDs]
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H03K 19/17732 Macroblocks
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/1774 for global signals, e.g. clock, reset
• CPC Class Codes: H03K 19/17744 for input/output signals
• CPC Class Codes: H03K 19/1776 for memories
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks

Abstract

A configurable logic array may include: a multiplicity of logic cells, containing look-up tables; customizable metal and via connection layers overlying the multiplicity of logic cells; a multiplicity of device customizable I/O cells; a multiplicity of configuration customizable RAM blocks; a ROM block with customizable contents; and a microprocessor with customizable I/O for configuring and testing the array, where the customizations are all done on a single via layer.

Claims

1. A semiconductor device comprising:

a logic array, said logic array including a multiplicity of logic cells,

said logic array further including metal and via connection layers overlying the multiplicity of logic cells for providing at least one permanent customized interconnect between various inputs and outputs thereof, wherein said customized interconnect is customized by a custom via layer; and

a multiplicity of device customized I/O cells, wherein said customized I/O cells are customized by said custom via layer, and wherein said I/O cells comprise at least three rows of pads.

2. The semiconductor device according to claim 1, wherein at least one row of pads is dedicated to provide at least one power connection to said logic array.

3. A semiconductor device comprising:

a logic array, said logic array including a multiplicity of logic cells,

said logic array further including metal and via connection layers overlying the multiplicity of logic cells for providing at least one permanent customized interconnect between various inputs and outputs thereof, wherein said customized interconnect is customized by a custom via layer; and

a customizable clock distribution structure, wherein said customizable clock distribution structure comprises at least one of the components selected from the group consisting of;

a customizable trimmer cell to fine tune said clock distribution structure'"'"'s delay, wherein said customizable trimmer cell is customized by said custom via layer; and

customizable connections to a phase lock loop circuit, wherein said customizable connections determine the phase and frequency of each clock.