Method and apparatus for clock and power control in wireless systems
First Claim
1. A baseband processor for wireless applications, comprising:
- a first module requiring a first clock signal derived from a system oscillator, the first module providing a first indicator signal having a first state which indicates that the first clock signal is required and a second state which indicates that the first clock signal is not required;
a second module requiring a second clock signal derived from the system oscillator, the second module providing a second indicator signal having a first state which indicates that the second clock signal is required and a second state which indicates that the second clock signal is not required; and
a power management circuit responsive to the first and second indicator signals for disabling the system oscillator when the first indicator signal is in the second state and the second indicator signal is in the second state and responsive to an enable signal for enabling the system oscillator.
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Accused Products
Abstract
A digital baseband processor is provided which receives a system clock generated by a system oscillator and generates a plurality of clock signals from the system clock. The digital baseband processor includes a digital signal processor for executing digital signal processor instructions, a microcontroller for executing microcontroller instructions, and other modules which may require one of the plurality of clock signals for operation. The digital baseband processor also includes a power management circuit which may power down the system oscillator when modules such as the digital signal processor and microcontroller do not require clock signals derived from the system oscillator. The power management circuit may gate off clock signals to modules when those modules do not require clock signals, without powering down the system oscillator.
29 Citations
43 Claims
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1. A baseband processor for wireless applications, comprising:
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a first module requiring a first clock signal derived from a system oscillator, the first module providing a first indicator signal having a first state which indicates that the first clock signal is required and a second state which indicates that the first clock signal is not required; a second module requiring a second clock signal derived from the system oscillator, the second module providing a second indicator signal having a first state which indicates that the second clock signal is required and a second state which indicates that the second clock signal is not required; and a power management circuit responsive to the first and second indicator signals for disabling the system oscillator when the first indicator signal is in the second state and the second indicator signal is in the second state and responsive to an enable signal for enabling the system oscillator. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25)
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26. In a baseband processor for wireless applications a method comprising:
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receiving a first indicator signal from a first module requiring a first clock signal derived from a system oscillator, the first indicator signal having a first state which indicates that the first clock signal is required and a second state which indicates that the first clock signal is not required; receiving a second indicator signal from a second module requiring a second clock signal derived from the system oscillator, the second indicator signal having a first state which indicates that the second clock signal is required and a second state which indicates that the second clock signal is not required; disabling the system oscillator when the first indicator signal is the second state and the second indicator signal is in the second state; and enabling the system oscillator when system oscillator output is required by at least one of the group comprising the first module and the second module. - View Dependent Claims (27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43)
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Specification