Method and apparatus for configuring a peripheral bus

• US 7,162,554 B1
• Filed: 07/11/2001
• Issued: 01/09/2007
• Est. Priority Date: 07/11/2001
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Cole, Terry Lynn, Gulick, Dale E., Barth, Frank, Winkler, Joerg, Maleck, Timothy C.
• Primary Examiner(s): AUVE, GLENN ALLEN
• Application Number:
  US09/904,373
• Time in Patent Office: 2,008 Days
• Field of Search: 713/1, 713/2, 713/100, 710/8, 710/10, 710/104, 710/62
• US Class Current: 710/104
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices

Abstract

A method an apparatus for providing capability information to a shared controller. In one embodiment, a peripheral bus host controller may be shared by a plurality of peripheral devices coupled to a peripheral bus. The peripheral devices may include coder/decoder (codec) circuitry, and may be implemented using a riser card. The host controller may be configured to query the bus for peripheral devices by reading each address on the bus. During the querying process, the host controller may detect one or more peripheral devices coupled to the bus. Following the completion of the querying of the bus, the host controller may then begin reading configuration information from each of the detected devices. The host controller may employ one or more of several different techniques in order to read configuration information from the peripheral device. The configuration information at a minimum includes a device identifier, which may identify the vendor and the function of the device. Additional information needed to configure the device to communicate over the peripheral bus may also be obtained with a read of the device, or various lookup mechanisms, such as a lookup table or a tree-like data structure. After configuration information has been obtained for each device coupled to the bus, the host controller may dynamically configure each of the devices for communication over the bus, thereby allowing the flexibility to enumerate riser cards and add new functions through peripheral devices to the computer system in which the bus is implemented.

Claims

1. A method for configuring a peripheral bus, the method comprising:

querying the peripheral bus, said querying including reading each possible address on the peripheral bus;

determining the presence of a peripheral device at an address on the peripheral bus;

reading configuration information from the peripheral device, wherein the configuration information includes device identification information, wherein said reading is performed over a serial side bus, wherein the serial side bus is separate from the peripheral bus, wherein the serial side bus is coupled to the host controller and the peripheral device; and

configuring the peripheral bus, said configuring including programming the peripheral device to use one or more timeslots;

wherein said querying, said determining, said reading, and said configuring are performed by a host controller coupled to the peripheral bus.

2. The method as recited in claim 1, wherein the peripheral bus is a serial bus.

3. The method as recited in claim 1, wherein the configuration information further includes one or more of the following:

quantity of timeslots needed by the peripheral device;

position of timeslots needed by the peripheral device;

data width of the peripheral device;

supported peripheral modes;

amount of buffer memory available in the peripheral device;

data format required by the peripheral device;

amount of I/O space required on higher layer system buses; and

clocking information.

4. The method as recited in claim 3, wherein the clocking information includes a determination of whether a peripheral device clock is a master clock or a slave clock.

5. The method as recited in claim 3, wherein the configuration information is passed from the peripheral device to the host controller by a single serial read.

6. The method as recited in claim 3 further comprising the host controller reading device identification information from the peripheral device, and obtaining additional configuration information from a lookup table.

7. The method as recited in claim 1 further comprising storing the configuration information from the peripheral device in a serial erasable programmable read-only memory (EPROM).

8. The method as recited in claim 1, wherein the device identification information includes vendor identification and function of the peripheral device.

9. The method as recited in claim 1, wherein the peripheral device is plug and play compatible.

10. The method as recited in claim 1 further comprising performing said querying, said determining, said reading, and said configuring for one or more additional peripheral devices coupled to the peripheral bus.

11. A computer system comprising:

a host controller;

a peripheral device coupled to the host controller by a peripheral bus;

wherein the host controller is configured to;

query a peripheral bus, wherein querying includes reading each possible address on the peripheral bus;

determine the presence of the peripheral device at an address on the peripheral bus;

read configuration information from the peripheral device, wherein the configuration information includes device identification information, wherein configuration information is read by the host controller over a serial side bus, wherein the serial side bus is separate from the peripheral bus, wherein the serial side bus is coupled to the host controller and the peripheral device;

configure the peripheral bus, wherein configuring the bus includes programming the peripheral device to use one or more timeslots.

12. The computer system as recited in claim 11, wherein the peripheral bus is a serial bus.

13. The computer system as recited in claim 11, wherein the configuration information further includes one or more of the following:

quantity of timeslots needed by the peripheral device;

position of timeslots needed by the peripheral device;

data width of the peripheral device;

supported peripheral modes;

amount of buffer memory available in the peripheral device;

data format required by the peripheral device;

amount of I/O space required on higher layer system buses; and

clocking information.

14. The computer system as recited in claim 13, wherein the clocking information includes a determination of whether a peripheral device clock is a master clock or a slave clock.

15. The computer system as recited in claim 13, wherein the configuration information is passed from the peripheral device to the host controller by a single serial read.

16. The computer system as recited in claim 13, wherein the host controller is configured to read device identification information from the peripheral device, and obtain additional configuration information from a lookup table.

17. The computer system as recited in claim 11 further comprising a serial erasable programmable read only memory (EPROM) configured to store the configuration information from the peripheral device.

18. The computer system as recited in claim 11, wherein the device identification information includes vendor identification and function of the peripheral device.

19. The computer system as recited in claim 11, wherein the host controller is further configured to query the peripheral bus for additional peripheral devices, and upon detection of an additional peripheral device, to read configuration information from the additional peripheral device, and reconfigure the bus, wherein reconfiguring the bus includes programming the additional peripheral device to use one or more timeslots.