Network delay identification method and apparatus
First Claim
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1. A method for identifying network delay, comprising:
- receiving tones that represent a sequence of bits, one of the bits identified as a reference bit;
sampling the tones beginning at a selected sample start time;
demodulating the tone samples to identify the bit values in a synchronization flag;
synchronizing with the tone samples by shifting the sample start time until the tone samples generate an optimum synchronization value; and
deriving a reference time according to the reference bit at the optimum synchronization value.
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Abstract
Network delay is determined in order to synchronize a clock in a mobile station with a reference clock. Tone are generated that represent a sequence of bits in a synchronization flag. The tones are sampled beginning at a selected sample start time. The sampled tones are demodulated to identify the bit values in the synchronization flag. The demodulator is synchronized with the sampled tones in the synchronization flag by shifting the sample start time until the samples generate an optimum synchronization value. A reference time is then identified according to the optimum sample start time.
125 Citations
14 Claims
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1. A method for identifying network delay, comprising:
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receiving tones that represent a sequence of bits, one of the bits identified as a reference bit; sampling the tones beginning at a selected sample start time; demodulating the tone samples to identify the bit values in a synchronization flag; synchronizing with the tone samples by shifting the sample start time until the tone samples generate an optimum synchronization value; and deriving a reference time according to the reference bit at the optimum synchronization value. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A computer readable medium containing code executable on a processor for identifying network delay in a communications network the stored code comprising:
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code for controlling the processor to receive tones that represent a sequence of bits; code for controlling the processor to sample the tones beginning at a selected sample start time; code for controlling the processor to demodulate the sampled tones back into bit values representing the sequence of bits; code for controlling the processor to synchronize with the sequence of bits by shifting the sample start time until the sampled tones generate an optimum synchronization value; and code for controlling the processor to derive a reference time according to the sample start time at the optimum synchronization value. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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Specification