Method and apparatus for generating an oversampling clock signal
First Claim
1. A method of determining oversampling timing from a reference clock source for an input symbol stream, said method comprising the steps of:
- enabling reference clock cycles periodically an integer number of times during each symbol period, each reference clock cycle enabled resulting in a sampling instance;
enabling reference clock cycles zero or more additional times each symbol period to produce a minimum number of sampling instances per symbol period;
delaying sampling instances zero or more compensation reference clock cycles during each averaging period consisting of one or more symbol periods; and
wherein the timing of said sampling instances is controlled in accordance with the following wherein A is the averaging period representing the minimum number that can be represented by an integer number of periods of said reference clock, fREF is the reference clock frequency, P is the symbol clock period, N is the number of chip steps in a symbol period, SBR is the symbol boundary remainder, and K is the number of compensation reference clock cycles to be added over the averaging period.
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Abstract
A timing estimation mechanism operative to generate an oversampling clock signal for a large range of reference clock frequencies without requiring use of a PLL. The oversampling timing mechanism generates appropriate timing instances, typically for the purpose of sampling a received data signal in a digital communications system, without requiring a specific external clock source but rather by utilizing a clock source having any arbitrary frequency. The mechanism of the present invention is especially suited for use in applications where a specific external clock source (e.g., integer multiple of the data rate) is not available and wherein the implications of the use of a PLL cannot be tolerated. The oversampling clock estimation mechanism generates a clock signal which may be unevenly distributed over the symbol period, but whereby on average, the correct number of samples is produced over a specific time duration.
14 Citations
22 Claims
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1. A method of determining oversampling timing from a reference clock source for an input symbol stream, said method comprising the steps of:
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enabling reference clock cycles periodically an integer number of times during each symbol period, each reference clock cycle enabled resulting in a sampling instance; enabling reference clock cycles zero or more additional times each symbol period to produce a minimum number of sampling instances per symbol period; delaying sampling instances zero or more compensation reference clock cycles during each averaging period consisting of one or more symbol periods; and wherein the timing of said sampling instances is controlled in accordance with the following wherein A is the averaging period representing the minimum number that can be represented by an integer number of periods of said reference clock, fREF is the reference clock frequency, P is the symbol clock period, N is the number of chip steps in a symbol period, SBR is the symbol boundary remainder, and K is the number of compensation reference clock cycles to be added over the averaging period. - View Dependent Claims (2, 3)
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4. A method of determining oversampling timing from a reference clock source for an input symbol stream, said method comprising the steps of:
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enabling reference clock cycles a predetermined number of times during each symbol period; injecting a controlled amount of jitter into said oversampling timing by enabling zero or more additional reference clock cycles each symbol period; and correcting any accumulated drift in said oversampling timing by enabling zero or more additional reference clock cycles after each averaging period of symbol times. - View Dependent Claims (5, 6, 7)
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8. An apparatus for generating oversampling timing from a reference clock source, comprising:
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a chip-step counter adapted to be clocked via said reference clock source and to generate a first terminal count every chip-step cycles of said reference clock; an N step counter adapted to be clocked by said first terminal count signal and to generate a second terminal count every N chip steps, wherein N is a positive integer; an averaging counter clock adapted to be clocked by said second terminal count signal and to generate a third terminal count signal every averaging period number of N chip steps; a drift lookup table coupled to the output of said averaging counter and operative to indicate a number of compensation cycles to be added over each averaging period; means for inserting zero or more reference clock cycles during each symbol period; and means for inserting zero or more compensation reference clock cycles as indicated by said drift lookup table over each averaging period. - View Dependent Claims (9, 10, 11)
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12. An apparatus for generating oversampling timing from a reference clock source for an input symbol stream, comprising:
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means for enabling reference clock cycles a predetermined number of times during each symbol period; means for injecting a controlled amount of jitter into said oversampling timing by enabling zero or more additional reference clock cycles each symbol period; and means for correcting any accumulated drift in said oversampling timing by enabling zero or more additional reference clock cycles after each averaging period of symbol times. - View Dependent Claims (13, 14)
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15. A correlator for recovering the timing from an input symbol stream, comprising:
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a plurality of symbol correlator cells, each symbol correlator cell comprising a plurality of data registers clocked by an oversampling clock and adapted to latch input samples spanning a symbol duration, wherein the number of input samples is dynamically set in accordance with an oversampling ratio signal; means for latching an input data sample either on the rising or falling edge of a reference clock in accordance with an edge select signal; means for generating an oversampling enable for enabling said plurality of data registers in each symbol correlator cell, said means comprising; means for enabling reference clock cycles a predetermined number of times during each symbol period; means for injecting a controlled amount of jitter into said oversampling timing by enabling zero or more additional reference clock cycles each symbol period; means for correcting any accumulated drift in said oversampling timing by enabling zero or more additional reference clock cycles after each averaging period of symbol times; and means for correlating said plurality of input samples with a reference value to generate a correlation result therefrom. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22)
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Specification