Multi-bit-per-cell flash EEPROM memory with refresh

• US 7,170,781 B2
• Filed: 04/07/2005
• Issued: 01/30/2007
• Est. Priority Date: 09/08/1997
• Status: Expired due to Fees

• Current Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: So, Hock C., Wong, Sau C.
• Primary Examiner(s): Lam; David
• Application Number:
  US11/101,938
• Publication Number:
  US 20050174844A1
• Time in Patent Office: 663 Days
• Field of Search: 365/185.03, 365/185.18, 365/185.24
• US Class Current: 365/185.03
• CPC Class Codes: B64C 27/006 Safety devices
• CPC Class Codes: G01N 29/14 using acoustic emission techniques echo of particles G01N29/046; measuring mechanical vibrations or acoustic waves in solids in general G01H1/00
• CPC Class Codes: G01N 29/227 related to high pressure, tension or stress conditions
• CPC Class Codes: G06F 11/106 Correcting systematically all correctable errors, i.e. scrubbing
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3431 Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2211/5634 Reference cells
• CPC Class Codes: G11C 29/00 Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/50004 of threshold voltage

Abstract

A multibit-per-cell non-volatile memory divides the suitable threshold voltages of memory cells into ranges corresponding to allowed states for storage of data and ranges corresponding to forbidden zones indicating a data error. A read process in accordance automatically checks whether a threshold voltage is in a forbidden zone. In an alternative embodiment, a refresh process includes reprogramming the threshold voltage into an allowed state. In the case of a flash memory, a refresh reads a sector of the memory and saves corrected data from the sector in a buffer or another sector. The corrected data from the buffer or other sector can be written back in the original sector, or the corrected data can be left in the other sector with addresses of the original sector being mapped to the other sector. Refresh process for the non-volatile memory can be perform in response to detecting a threshold voltage in a forbidden zone, as part of a power-up procedure for the memory, or periodically with a period on the order of days, weeks, or months. As a further aspect, the allowed states correspond to gray coded digital values so that allowed states that are adjacent in threshold voltage correspond to multibit values that differ in only a single bit. Error detection and correction codes can be used to identify data errors and generate corrected data for refresh operations.

Claims

1. A non-volatile semiconductor memory comprising:

an array of memory cells;

drivers and decoders coupled to apply voltages to the array, as required to write to any memory cell in the array and to read any memory cell in the array, wherein each memory cell that stores data has a threshold voltage that identifies a multibit data value written in the memory cell;

a reference generator that generates first reference signals and second reference signals, wherein the first reference signals indicate bounds of allowed ranges of threshold voltages corresponding to data values that can be stored in the memory cell, and the second reference signals indicate bounds of one or more forbidden ranges of threshold voltages corresponding to data errors, wherein the allowed ranges of threshold voltages are separated from each other by at least one forbidden range; and

a control circuit coupled to control the drivers and decoders during a read process, the control circuit including logic that initiates a process to refresh a threshold voltage of a memory cell when a read process that detects that the threshold voltage of the memory cell is in a forbidden range.

2. The non-volatile memory of claim 1, further comprising a timer that triggers a refresh operation by initiating reading of at least a portion of the memory array.

3. The non-volatile memory of claim 2, wherein the array, the drivers and decoders, the reference generator, the control circuit, the timer are parts of a monolithic integrated circuit.

4. The non-volatile memory of claim 2, further comprising a buffer coupled to temporarily store data from the portion of the memory array, during the refresh operation.

5. A method for operating a non-volatile memory, comprising:

programming threshold voltages of memory cells in the non-volatile memory so that each memory cell has a threshold voltage in an allowed state associated with a multibit data value stored in the memory cell, wherein threshold voltages of the memory cells have a plurality of allowed ranges of threshold voltages corresponding to data values that can be stored in the memory cell that are separated from each other by forbidden zones of threshold voltages corresponding to data errors;

identifying a portion of the non-volatile memory that contains a memory cell with a threshold voltage in one of the forbidden zones; and

refreshing the multibit data values stored in memory cells in the identified portion by reprogramming the threshold voltages.

6. The method of claim 5, wherein refreshing the multibit data values is performed in response to a signal from a timer.

7. The method of claim 6, wherein refreshing the multibit data values is performed periodically with a period greater than one day.

8. The method of claim 6, further comprising determining a time during which use of the memory is unlikely, wherein the timer schedules refreshing for that time.

9. The method of claim 5, wherein refreshing the multibit data values is performed as part of a power up procedure for the memory.

10. The method of claim 5, wherein the portion identified as containing a memory cell with a threshold voltage in one of the forbidden zones is a sector, and refreshing the multibit data values comprises:

reading data values from the sector;

storing the data values in a buffer;

erasing the sector; and

writing the data values back in the sector.

11. The method of claim 5, wherein reading the data values comprises measuring the threshold voltage of the memory cell with the threshold voltage in one of the forbidden zones, wherein a data value read from that memory cell corresponds to an allowed state near the forbidden zone containing the threshold voltage of the memory cell.