Method, system and memory controller utilizing adjustable read data delay settings

CAFC
  • US 7,177,998 B2
  • Filed: 01/18/2006
  • Issued: 02/13/2007
  • Est. Priority Date: 04/24/2001
  • Status: Expired due to Term
First Claim
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1. A system comprising:

  • a first memory device and a second memory device;

    a control signal path coupled to the first memory device and the second memory device such that a read command propagating on the control signal path propagates past the first memory device before reaching the second memory device and such that a first propagation time required for the read command to propagate on the control signal path from the memory controller to the first memory device is different than a second propagation time required for the read command to propagate on the control signal path from the memory controller to the second memory device;

    a first signal line coupled to the first memory device to convey first data output from the first memory device in response to the read command;

    a second signal line coupled to the second memory device to convey second data output from the second memory device in response to the read command; and

    a memory controller including;

    a first circuit to receive the first data from the first memory device after delaying for a first time interval that is based, at least in part, on the first propagation time; and

    a second circuit to receive the second data from the second memory device after delaying for a second time interval that is based, at least in part, on the second propagation time.

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