State retention within a data processing system

• US 7,183,825 B2
• Filed: 04/06/2004
• Issued: 02/27/2007
• Est. Priority Date: 04/06/2004
• Status: Active Grant

• Current Assignee: VLSI Technology LLC (SoftBank Group Corp.)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Gupta, Sanjay, Yuan, Yuan, Chun, Christopher K. Y., Padhye, Milind P.
• Primary Examiner(s): Lam, Tuan T.
• Assistant Examiner(s): Nguyen, Hiep
• Application Number:
  US10/818,861
• Publication Number:
  US 20050218952A1
• Time in Patent Office: 1,057 Days
• Field of Search: 327/202, 327/203, 327/204, 327/205, 327/206, 327/207
• US Class Current: 327/202
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence

Abstract

Power consumption may be reduced through the use of power gating in which power is removed from circuit blocks or portions of circuit blocks in order to reduce leakage current. One embodiment uses a modified state retention flip-flop capable of retaining state when power is removed or partially removed from the circuit. Another embodiment uses a modified state retention buffer capable of retaining state when power is removed or partially removed from the circuit. The state retention flip-flop and buffer may be used to allow for state retention while still reducing leakage current. Also disclosed are various methods of reducing power and retaining state using, for example, the state retention flip-flops and buffers. For example, software, hardware, or a combination of software and hardware methods may be used to enter a deep sleep or idle mode while retaining state.

Claims

1. A circuit comprising a state-retentive flip-flop, the flip-flop comprising:

input and output nodes;

two latches, a master latch and a slave latch, each of the latches including a circuit element coupled in series with the input and output nodes, a first one of the latches being configured to retain a state of the flip-flop during a power managed mode in which power is decoupled from a second one of the latches;

a switch controller coupled to receive a clock signal and a power gate indicator signal, the switch controller generating a first set of switch control values dependent upon the clock signal when the power gate indicator signal has a first value and generating a second set of switch control values independent of the clock signal when the power gate indicator signal has a second value;

a first switch coupled between the input node and the master latch; and

a second switch coupled between the master latch and the slave latch, wherein

the switch controller is coupled to provide switch control signals to the first and second switches;

and wherein;

the master latch includes cross-coupled invertors and a third switch, one of the invertors and the third switch being coupled to the first switch, the third switch being coupled to receive a switch control signal from the switch controller; and

the slave latch includes cross-coupled invertors and a fourth switch, one of the invertors of the slave latch and the fourth switch being coupled to the second switch, each of the invertors of the slave latch being coupled to the output node, the fourth switch being coupled to receive a switch control signal from the switch controller, wherein an input of the slave latch located between the second switch and the one of the invertors of the slave latch is not provided as feedback to the master latch during the power managed mode.

2. The circuit of claim 1 wherein:

the switch controller is configured to control the first and fourth switches to a first switch state and the second and third switches to a second switch state responsive to the clock signal having a first value and the power gate indicator signal having a first value;

the switch controller is configured to control the first and fourth switches to the second state and the second and third switches to the first state responsive to the clock signal having a second value and the power gate indicator signal having the first value; and

the switch controller is configured to control the first and second switches to a first state and the third and fourth switches to a second state responsive to the power gate indicator signal having a second value.

3. The circuit of claim 1, the flip-flop further comprising:

a clock signal input node for receiving a clock signal; and

a power gate indicator input node for receiving a power gate indicator signal, the flip-flop operating in a first operational state dependent upon the clock signal when the power gate indicator signal has a first value and operating in a second operational state independent from the clock signal when the power gate indicator signal has a second value, the second operational state retaining the state of the flip-flop while expending less power than the first operational state.

4. The circuit of claim 1, the flip-flop further comprising:

a first power supply node coupled to receive a continuous power supply signal; and

a second power supply node coupled to receive a gated power supply signal.

5. The circuit of claim 4 wherein:

the state-retentive flip-flop is a positive-edge flip-flop;

the slave latch is coupled to receive the continuous power supply signal via the first power supply node; and

the master latch is coupled to receive the gated power supply signal via the second power supply node.

6. The circuit of claim 4 wherein:

the state-retentive flip-flop is a negative-edge flip-flop;

the master latch is coupled to receive the continuous power supply signal via the first power supply node; and

the slave latch is coupled to receive the gated power supply signal via the second power supply node.

7. The circuit of claim 1 wherein

the state-retentive flip-flop is a positive-edge flip-flop;

the first one of the latches is the slave latch; and

the second one of the latches is the master latch.

8. The circuit of claim 7 further comprising a negative edge flip-flop, the negative edge flip-flop comprising:

input and output nodes; and

two latches, a master latch and a slave latch, each of the latches of the negative edge flip-flop including a circuit element coupled in series with the input and output nodes of the negative edge flip-flop, the master latch of the negative edge flip-flop being configured to retain a state of the flip-flop during a power managed mode in which power is decoupled from the slave latch of the negative edge flip-flop.

9. The circuit of claim 1,

the switch controller is configured to control the first and fourth switches to a first switch state and the second and third switches to a second switch state responsive to the clock signal having a first value and the power gate indicator signal having a first value;

the switch controller is configured to control the first and fourth switches to the second state and the second and third switches to the first state responsive to the clock signal having a second value and the power gate indicator signal having the first value; and

the switch controller is configured to control the third and fourth switches to the first switch state and the first and second switches to the second state responsive to the power gate indicator signal having a second value.

10. A circuit comprising a state-retentive flip-flop, the flip-flop comprising:

input and output nodes; and

two latches, a master latch and a slave latch, each of the latches including a circuit element coupled in series with the input and output nodes, a first one of the latches being configured to retain a state of the flip-flop during a power managed mode in which power is decoupled from a second one of the latches;

and wherein the circuit further comprises;

a clock controller coupled to receive a reference clock and to provide a run clock and a sleep clock;

run domain circuitry including a non-state-retentive flip-flop, the non-state-retentive flip-flop being coupled to receive the run clock signal; and

sleep domain circuitry including the state-retentive flip-flop being coupled to receive the sleep clock signal.

11. The circuit of claim 10 further comprising:

a state retention controller coupled to provide a power gate indicator signal to the sleep domain circuitry and to provide a power gate control signal to a power gating switch; and

the power gating switch coupled to receive a continuous power supply signal and to provide a gated power supply signal to the sleep domain circuitry under control of the power gate control signal.

12. A method of reducing power loss in an information processing system having running domain circuitry and sleep domain circuitry, the method comprising:

receiving a power gate request for diminishing power loss in the information processing system;

disabling a sleep domain clock coupled to the sleep domain circuitry

saving a current state of corresponding sleep domain circuitry in at least one of two series coupled latches in each flip-flop of the sleep domain circuitry;

regulating a supply voltage from at least a portion of sleep domain circuitry corresponding to the power gate request,

wherein the step of disabling the sleep domain clock includes confirming that the sleep clock is disabled before regulating the supply voltage of the sleep domain circuitry.

13. The method of claim 12 wherein the power gate request is a partial gate request, and the step of receiving the gate request includes identifying a specific portion of the sleep domain circuitry.

14. The method of claim 12 wherein the step of regulating the supply voltage of the sleep domain circuitry comprises at least one of the following steps:

decoupling power from the sleep domain circuitry;

or

reducing power to the sleep domain circuitry.

15. The method of claim 12 further comprising:

receiving an additional power gate request; and

repeating the steps of disabling, confirming and saving responsive to receiving the additional power gate request.

16. The method of claim 12 further comprising:

reducing a supply voltage to the running domain circuitry and any sleep domain circuitry still operating.

17. The method of claim 12 further comprising:

receiving a global or a partial power gate exit request;

restoring the supply voltage to the running domain and sleep domain circuitry;

restoring the state of the sleep domain circuitry; and

enabling the sleep domain clock.

18. The method of claim 12 wherein the step of restoring the state of the sleep domain circuitry includes restoring a higher power level to the sleep domain circuitry and enabling the sleep domain circuitry to operate according to the sleep clock.

19. The method of claim 12 wherein the step of saving the current state of corresponding sleep domain circuitry comprises:

saving the current state in a master latch of each flip-flop for which a received clock signal stops in a first state; and

saving the current state in a slave latch of each flip-flop for which a received clock signal stops in a second state.

20. The method of claim 19 wherein the first state is a logic zero and the second state is a logic one.