Apparatus and method for selective control of condition code write back

• US 7,185,180 B2
• Filed: 05/09/2002
• Issued: 02/27/2007
• Est. Priority Date: 04/02/2002
• Status: Expired due to Term

• Current Assignee: IP-First LLC, Centaur Technology (VIA Technologies)
• Original Assignee: IP-First LLC
• Inventors: Parks, Terry, Henry, G. Glenn, Hooker, Rodney E.
• Primary Examiner(s): MOLL, JESSE R
• Application Number:
  US10/144,593
• Publication Number:
  US 20030188133A1
• Time in Patent Office: 1,755 Days
• Field of Search: 712/218, 712/209, 712/212, 712/226, 712/210, 711/108, 711/102
• US Class Current: 712/218
• CPC Class Codes: G06F 9/30094 Condition code generation, e.g. Carry, Zero flag
• CPC Class Codes: G06F 9/30185 according to one or more bits in the instruction, e.g. prefix, sub-opcode
• CPC Class Codes: G06F 9/30189 according to execution mode, e.g. mode flag
• CPC Class Codes: G06F 9/3842 Speculative instruction execution

Abstract

A microprocessor apparatus and method are provided, for selectively controlling write back of condition codes. The microprocessor apparatus has translation logic and extended execution logic. The translation logic translates an extended instruction into corresponding micro instructions. The extended instruction includes an extended prefix and an extended prefix tag. The extended prefix disables write back of the condition codes, where the condition codes correspond to a result of a prescribed operation. The extended prefix tag indicates the extended prefix, where the extended prefix tag is an otherwise architecturally specified opcode within an instruction set for a microprocessor. The extended execution logic is coupled to the translation logic. The extended execution logic receives the corresponding micro instructions, and generates the result, and disables write back of the condition codes.

Claims

1. A microprocessor apparatus, for selectively controlling write back of condition codes, comprising:

translation logic, for translating an extended instruction into corresponding micro instructions, wherein said extended instruction comprises;

an extended prefix, for disabling write back of the condition codes, the condition codes corresponding to a result of a prescribed operation; and

an extended prefix tag, for indicating said extended prefix, wherein said extended prefix tag is an otherwise architecturally specified opcode within an instruction set for a microprocessor; and

extended execution logic, coupled to said translation logic, for receiving said corresponding micro instructions, and for generating said result, and for disabling write back of the condition codes.

2. The microprocessor apparatus as recited in claim 1, wherein said extended instruction further comprises architecturally specified entities according to said instruction set.

3. The microprocessor apparatus as recited in claim 2, wherein said architecturally specified entities comprise:

an opcode entity, for specifying said prescribed operation.

4. The microprocessor apparatus as recited in claim 1, wherein said extended prefix comprises a plurality of bits, and wherein each logic state of said plurality of bits directs said microprocessor to disable write back of a subset of a plurality of result conditions, wherein the condition codes comprise a particular subset of said plurality of result conditions.

5. The microprocessor apparatus as recited in claim 4, wherein said plurality of result conditions comprises overflow, carry, zero, sign, and parity.

6. The microprocessor apparatus as recited in claim 5, wherein said plurality of result conditions are maintained in a flags register in said microprocessor.

7. The microprocessor apparatus as recited in claim 1, wherein said extended prefix comprises 8 bits.

8. The microprocessor apparatus as recited in claim 1, wherein said instruction set comprises the x86 instruction set.

9. The microprocessor apparatus as recited in claim 8, wherein said extended prefix tag comprises opcode F1 (ICE BKPT) in the x86 instruction set.

10. The microprocessor apparatus as recited in claim 1, wherein said corresponding micro instructions comprise a micro opcode field and a micro opcode extension field.

11. The microprocessor apparatus as recited in claim 10, wherein said extended execution logic employs said micro opcode extension field to determine the condition codes whose write back is to be disabled, and wherein said extended execution logic employs said micro opcode field to determine said prescribed operation to be executed, thereby generating said result.

12. The microprocessor apparatus as recited in claim 11, where said extended execution logic comprises:

a condition codes write back controller, configured to update a condition codes register following generation of operation results, and configured to preclude write back of the condition codes following generation of said result.

13. The microprocessor apparatus as recited in claim 1, wherein said translation logic comprises:

escape instruction detection logic, for detecting said extended prefix tag; and

extended prefix decoding logic, coupled to said escape instruction detection logic, for translating said extended prefix, and for configuring a micro opcode extension field within said corresponding micro instructions, said micro opcode extension field prescribing the condition codes whose write back is to be disabled.

14. The microprocessor apparatus as recited in claim 13, wherein said translation logic further comprises:

instruction decoding logic, for configuring remaining fields within said corresponding micro instructions, said remaining fields specifying said prescribed operation according to said instruction set.

15. An extension mechanism, for adding condition flags write back control features to an existing microprocessor instruction set, the extension mechanism comprising:

an extended instruction, configured to direct a microprocessor to suppress write back of a subset of a plurality of condition flags, said plurality of condition flags reflecting boundary conditions of a result, said result corresponding to execution of a specified operation, wherein said extended instruction comprises a selected opcode in the existing microprocessor instruction set followed by an n-bit extended control prefix, said selected opcode indicating said extended instruction and said n-bit extended control prefix indicating said subset; and

a translator, configured to receive said extended instruction, and configured to generate a micro instruction sequence directing said microprocessor to execute said specified operation, and directing write back control logic to preclude write back of said subset following generation of said result.

16. The extension mechanism as recited in claim 15, wherein said extended instruction further comprises:

other extended instruction entities, configured to prescribe said specified operation.

17. The extension mechanism as recited in claim 16, wherein said other extended instruction entities are formatted in accordance with the existing microprocessor instruction set.

18. The extension mechanism as recited in claim 15, wherein said plurality of condition codes comprises overflow, carry, zero, sign, and parity.

19. The extension mechanism as recited in claim 15, wherein said n-bit extended control prefix comprises 8 bits.

20. The extension mechanism as recited in claim 15, wherein the existing microprocessor instruction set is the x86 microprocessor instruction set.

21. The extension mechanism as recited in claim 20, wherein said selected opcode comprises opcode ICE BKPT (i.e., opcode F1) in the x86 microprocessor instruction set.

22. The extension mechanism as recited in claim 15, wherein said translator comprises:

an escape instruction detector, for detecting said selected opcode within said extended instruction; and

an extended prefix decoder, coupled to said escape instruction detector, for translating said n-bit extended control prefix, and for generating a micro opcode extension field within said sequence of micro instructions that prescribes said subset.

23. An instruction set extension apparatus, for providing selective condition codes write back capabilities to an existing microprocessor instruction set, the instruction set extension apparatus comprising:

an escape tag, for reception by translation logic, and for indicating that accompanying parts of a corresponding instruction prescribe an extended operation to be performed by a microprocessor, wherein said escape tag is a first opcode entity within the existing microprocessor instruction set;

a codes write back specifier, coupled to said escape tag and being one of said accompanying parts, for prescribing a plurality of condition codes associated with a result of said extended operation; and

a condition codes write back controller, coupled to said translation logic, for disabling write back of said plurality of said condition codes, and for enabling write back of remaining ones of said condition codes.

24. The instruction set extension apparatus as recited in claim 23, wherein the remainder of said accompanying parts comprise a second opcode entity and an optional plurality of address specifier entities.

25. The instruction set extension apparatus as recited in claim 23, wherein said codes write back specifier comprises an 8-bit data entity.

26. The instruction set extension apparatus as recited in claim 23, wherein the existing microprocessor instruction set is the x86 microprocessor instruction set.

27. The instruction set extension apparatus as recited in claim 26, wherein said first opcode entity comprises the ICE BKPT opcode entity (i.e., opcode F1) in the x86 microprocessor instruction set.

28. The instruction set extension apparatus as recited in claim 23, wherein said translation logic translates said escape tag and said accompanying parts into corresponding micro instructions that direct extended execution logic to perform said extended operation.

29. The instruction set extension apparatus as recited in claim 23, wherein said translation logic comprises:

escape tag detection logic, for detecting said escape tag, and for directing that said accompanying parts be translated according to extended translation conventions; and

decoding logic, coupled to said escape tag detection logic, for performing translation of microprocessor instructions according to conventions of the existing microprocessor instruction set, and for performing translation of said corresponding instruction according to said extended translation conventions to allow selective write back of said condition codes.

30. A method for extending a microprocessor instruction set to provide for programmable write back of result condition codes, the method comprising:

providing an extended instruction, the extended instruction including an extended tag along with a condition codes write back prefix, wherein the extended tag is a first opcode in the microprocessor instruction set;

prescribing, via the condition codes write back prefix and remaining parts of the extended instruction, an operation to be executed, wherein write back of selected condition codes associated with a result of the operation is to be inhibited; and

executing the operation to generate the result, and inhibiting write back of the selected condition codes.

31. The method as recited in claim 30, wherein said prescribing comprises:

first specifying the operation, wherein said first specifying comprises employing a second opcode in the microprocessor instruction set.

32. The method as recited in claim 30, wherein said providing comprises employing an 8-bit entity to configure the condition codes write back prefix.

33. The method as recited in claim 30, wherein said providing comprises selecting the first opcode from the x86 microprocessor instruction set.

34. The method as recited in claim 33, wherein said selecting comprises choosing the x86 ICE BKPT opcode (i.e., opcode F1) as the extended tag.

35. The method as recited in claim 30, further comprising:

translating the extended instruction into micro instructions that direct extended execution logic to inhibit write back of the selected condition codes following said executing.

36. The method as recited in claim 35, wherein said translating comprises:

within translation logic, detecting the extended tag; and

decoding the condition specifier prefix and the remaining parts of the extended instruction according to extended translation rules, the extended translation rules providing programmable write back control capabilities to an existing microprocessor architecture which are not provided according to conventional translation rules.