Key caching system

• US 7,185,196 B1
• Filed: 09/15/2000
• Issued: 02/27/2007
• Est. Priority Date: 09/15/2000
• Status: Expired due to Fees

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Atheros Communications Incorporated (Qualcomm, Inc.)
• Inventors: Ng, Tao-Fei Samuel, Davidson, Andrew M., Kuskin, Jeffrey Scott, Dhamdhere, Deepak Prabhakar, Cain, Fiona J.
• Primary Examiner(s): Moazzami; Nasser
• Assistant Examiner(s): COLIN, CARL G
• Application Number:
  US09/662,991
• Time in Patent Office: 2,356 Days
• Field of Search: 455/564, 707/103.R, 711/164, 711/113, 711/3, 711/4, 711/122, 713/162, 713/200, 713/201, 713/189, 713/187, 395/425, 395/403, 395/200, 370/392, 709/225, 380/49, 380/28
• US Class Current: 713/162
• CPC Class Codes: H04L 1/1829 Arrangements specially adapted for the receiver end
• CPC Class Codes: H04L 61/35 involving non-standard use of addresses for implementing network functionalities, e.g. coding subscription information within the address or functional addressing, i.e. assigning an address to a function
• CPC Class Codes: H04L 63/0428 wherein the data content is protected, e.g. by encrypting or encapsulating the payload
• CPC Class Codes: H04L 63/062 for key distribution, e.g. centrally by trusted party cryptographic mechanisms or cryptographic arrangements for key distribution involving a central third party H04L9/0819
• CPC Class Codes: H04L 63/164 at the network layer
• CPC Class Codes: H04L 69/12 Protocol engines
• CPC Class Codes: H04L 9/40 Network security protocols
• CPC Class Codes: H04W 12/033 of the user plane, e.g. user's traffic
• CPC Class Codes: H04W 12/04 Key management, e.g. using generic bootstrapping architecture [GBA]
• CPC Class Codes: H04W 8/26 Network addressing or numbering for mobility support
• CPC Class Codes: H04W 84/12 WLAN [Wireless Local Area Networks]

Abstract

A key-caching system retrieves actively used keys from a relatively fast cache memory for fast processing of wireless communications. Additional keys are stored in relatively slow system memory that has high storage capacity. As keys become needed for active use, the keys are retrieved from the system memory and stored in the cache memory. By using active memory for keys actively being used, system performance is enhanced. By using system memory for keys not being used, a greater number of keys are available for transfer to the cache and subsequent active use.

Claims

1. Computer-readable media tangibly embodying a key-caching program executable on a computer and operating on a packet received from an external source, the computer including a system memory and a cache, the system memory and the cache including entries for source addresses and corresponding keys, the packet including a header that is not encrypted and a body that is encrypted, the key-caching program comprising code for:

establishing acknowledgment-responsive wireless communication with the external source wherein the packet is re-sent after a latency period in the absence of an acknowledgment signal for the packet;

extracting from the header a source address;

determining whether the source address is included in an entry in the cache;

when the source address is included in an entry of the cache, authorizing the acknowledgment signal for the external source, extracting from the entry of the cache a key corresponding to the source address, and using the key to decrypt the body of the packet;

when the source address is not included in an entry of the cache, determining whether the source address is included in an entry of the system memory; and

when the source address is not included in an entry of the cache and the source address is included in an entry of the system memory, extracting from the entry of the system memory a key corresponding to the source address, and storing the source address and the key as a new entry in the cache to prepare the cache within the latency period for decrypting the packet subsequently re-sent by the external source.

2. Computer-readable media as claimed in claim 1, wherein the key-caching program further comprises code to effect:

when the source address is not included in an entry of the cache, dropping the packet.

3. Computer-readable media as claimed in claim 2, wherein the cache includes fast memory.

4. Computer-readable media as claimed in claim 1, wherein the key-caching program further comprises code to effect:

when the source address is not included in an entry of the cache, authorizing an acknowledgment signal for anticipatory transmission to the external source of the packet prior to retrieval of the key corresponding to the source address; and

when the source address is not included in an entry of the cache and the source address is included in an entry of the system memory, using the key to decrypt the body of the packet prior to arrival of a subsequent packet from the external source.

5. Computer-readable media as claimed in claim 4, wherein the cache includes fast memory.

6. Computer-readable media as claimed in claim 1, wherein the cache includes fast memory.

7. A key-caching system for operation on a packet received from an external source, the packet comprising a header that is not encrypted and a body that is encrypted, the key-caching system comprising:

a system memory,

a networking unit, the networking unit including a cache, the system memory and the cache including entries for source addresses and corresponding keys,

a processor, the system memory including a key-caching program that is executable on the processor, and

a controller, the controller effecting communication and data transfer between the system memory, the networking unit and the processor, wherein the key-caching program comprising code to effect;

establishing acknowledgment-responsive wireless communication with the external source wherein the packet is re-sent after a latency period in the absence of an acknowledgement signal for the packet;

extracting from the header a source address;

determining whether the source address is included in an entry in the cache;

when the source address is included in an entry of the cache, authorizing the acknowledgment signal for the external source, extracting from the entry of the cache a key corresponding to the source address, and using the key to decrypt the body of the packet;

when the source address is not included in an entry of the cache, determining whether the source address is included in an entry of the system memory; and

when the source address is not included in an entry of the cache and the source address is included in an entry of the system memory, extracting from the entry of the system memory a key corresponding to the source address, and storing the source address and the key as a new entry in the cache to prepare the cache within the latency period for decrypting the packet subsequently re-sent by the external source.

8. A key-caching system as claimed in claim 7, wherein the key-caching program further comprises code to effect:

when the source address is not included in an entry of the cache, dropping the packet.

9. A key-caching system as claimed in claim 8, wherein the cache includes fast memory.

10. A key-caching system as claimed in claim 7, wherein the key-caching program further comprises code to effect:

when the source address is not included in an entry of the cache, authorizing an acknowledgment signal for anticipatory transmission to the external source of the packet prior to retrieval of the key corresponding to the source address; and

when the source address is not included in an entry of the cache and the source address is included in an entry of the system memory, using the key to decrypt the body of the packet prior to arrival of a subsequent packet from the external source.

11. A key-caching system as claimed in claim 9, wherein the cache includes fast memory.

12. A key-caching system as claimed in claim 7, wherein the cache includes fast memory.

13. A method of key caching with a system memory and a cache, the system memory and the cache including entries for source addresses and corresponding keys, the method comprising:

establishing acknowledgment-responsive wireless communication with an external source wherein the packet is re-sent after a latency period in the absence of an acknowledgment signal for the packet;

receiving a packet from the external source, the packet including a header that is not encrypted and a body that is encrypted;

extracting from the header a source address;

determining whether the source address is included in an entry in the cache, authorizing the acknowledgment signal for the external source when the source address is not included in an entry of the cache, extracting from the entry of the cache a key corresponding to the source address, and using the key to decrypt the body of the packet;

when the source address is not included in an entry of the cache, determining whether the source address is included in an entry of the system memory; and

when the source address is not included in an entry of the cache and the source address is included in an entry of the system memory, extracting from the entry of the system memory a key corresponding to the source address, and storing the source address and the key as a new entry in the cache to prepare the cache within the latency period for decrypting the packet subsequently re-sent by the external source.

14. A method of key caching as claimed in claim 13, further comprising:

when the source address is not included in an entry of the cache, dropping the packet.

15. A method of key caching as claimed in claim 14, wherein the cache includes fast memory.

16. A method of key caching as claimed in claim 13, further comprising:

when the source address is not included in an entry of the cache, authorizing an acknowledgment signal for anticipatory transmission to the external source of the packet prior to retrieval of the key corresponding to the source address; and

when the source address is not included in an entry of the cache and the source address is included in an entry of the system memory, using the key to decrypt the body of the packet prior to arrival of a subsequent packet from the external source.

17. A method of key caching as claimed in claim 16, wherein the cache includes fast memory.

18. A method of key caching as claimed in claim 13, wherein the cache includes fast memory.