SOI structure comprising substrate contacts on both sides of the box, and method for the production of such a structure

• US 7,195,961 B2
• Filed: 01/30/2004
• Issued: 03/27/2007
• Est. Priority Date: 01/30/2003
• Status: Active Grant

• Current Assignee: X-FAB Semiconductor Foundries AG (X-FAB Silicon Foundries SE)
• Original Assignee: X-FAB Semiconductor Foundries AG (X-FAB Silicon Foundries SE)
• Inventors: Richter, Steffen, Goettlich, Wolfgang, Nuernbergk, Dirk
• Primary Examiner(s): Coleman; W. David
• Application Number:
  US10/543,923
• Publication Number:
  US 20060154430A1
• Time in Patent Office: 1,152 Days
• Field of Search: 438/149, 438/151
• US Class Current: 438/151
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688

Abstract

Disclosed are an arrangement and a production method for electrically connecting (20) active semiconductor structures (40) in the monocrystalline silicon layer (12) located on the front face of silicon-on-insulator semiconductor wafers (SOI; 10) to the substrate (13) located on the rear side and additional structures (13a) that are disposed therein. The electric connection is made through the insulator layer (11).

Claims

1. A method for manufacturing an integrated circuit on and in an SOI semiconductor wafer having a front and a back, wherein first structures having active devices in an upper semiconductor layer (12) and second structures (13a, 13a′

, 13c) of devices within the substrate (13) are connected by electric connection (20, 22) formed through an insulating layer (11), the method comprising the following steps;

performing an ion implantation (30, 31) with highly energetic ions in certain areas (13′

, 13″

) from the front through the upper semiconductor layer (12), through the insulating layer (11) and into the substrate (13);

performing a temperature treatment for activating the ions implanted into the substrate (13) in accordance with an implanted ion species, wherein the implanted ions are activated in a plurality of steps with different temperatures;

forming the first structures (30, 40, 50, 60) at least partially in the upper semiconductor layer as a single crystalline layer (12);

forming at least one of a plurality of vias in the insulating layer (11);

filling (20, 22) the at least one via (19, 21) in the insulating layer with a metallic material to provide a metallic filling;

forming-in the area of the first structures (40, 50, 60) insulated with respect to each other-metal conductors to electrically connect the first structures of the front with the second structure within the substrate (13) via the at least on metal filling in the at least one via.

2. The method of claim 1, wherein the insulating layer (11) is a silicon dioxide layer.

3. The method of claim 1, wherein a single insulating layer (11) is provided, through which the metal filling extends.

4. The method of claim 1, wherein the upper layer (12) is a thin layer with respect to the substrate (13) of the SOI wafer (10).

5. The method of claim 1, wherein the steps of the method are performed in the order as given in claim 1.

6. The method of claim 1, wherein devices below the insulating layer (11) are formed by using templates and different ion species (30, 31).

7. The method of claim 1, wherein a plurality of vias is filled with a plurality of metallic fillings.

8. The method of claim 1, wherein the vias are formed at locations at which no active single crystalline layer (12) is present, in the form of lateral insulation areas).

9. The method of claim 1, wherein the upper semiconductor layer (12) is comprised of silicon.

10. The method of claim 1, wherein the first structures (40) are at least partially formed in the upper silicon layer.

11. The method of claim 1, wherein the substrate (13) is comprised of a single crystalline silicon.

12. The method of claim 1, wherein simultaneously with the process of forming the at least one filling of the at least one via (19, 21), an ohmic contact (13B) or a conductive conductor to the substrate is formed.

13. The method of claim 1, wherein simultaneously with the process of forming the filling of the at least one via (19, 21), a Schottky contact (13C) is formed with the substrate (13).

14. The method of claim 1, wherein two first structures for two first devices (40, 50) above the insulating layer (11) are separated and insulated by at least one trench extending towards the insulating layer.

15. The method of claim 1, wherein a back side metallization (14) is formed on the back of the SOI semiconductor wafer.

16. The method of claim 1, wherein the metal conductors (15, 15′

) are metallization layers.

17. The method of claim 16, wherein the metal conductors are provided in the form of metal bridges on at least two non-identical levels above the insulating layer.

18. A method for forming an integrated circuit with a SOI semiconductor wafer, active device structures in a thin upper crystalline semiconductor layer being connected with device structures within substrate by means of electrical connections formed through the insulating layer, wherein a sequence of main method steps is performed

in specified areas, performing an ion implantation with highly energetic ions from the front through the single crystalline semiconductor layer and the insulating layer into the substrate;

performing a temperature treatment for activating the implanted ions in several steps of different temperatures, adapted to the ion species implanted;

forming upper device structures in the single crystalline layer;

forming vias in the insulating layer at locations where no active thin single crystalline silicon layer is present;

filling the vias in the insulating layer with a metallic material;

forming metallization layers, insulated from each other within the area of the active device structures and electrically connecting the upper structures with those device structures within the substrate by means of the metal filling in said vias in the insulating layer.

19. The method of claim 18, wherein the insulating layer is a layer of silicon dioxide.

20. The method of claim 18, wherein independent bridges are provided to contact the metal fillings in said vias.

21. The method of claim 18, wherein a back side metallization (14) is provided on the substrate (13).

22. The method of claim 18, wherein the substrate is comprised of a single crystalline silicon wafer.

23. The method of claim 18, wherein along with the process of forming a metal bridge of one of the vias, an ohmic contact to the substrate is formed.

24. The method of claim 18, wherein along with the process of forming a respective metal bridge of a respective via, a Schottky contact with the substrate is formed.

25. A method for forming an integrated circuit with a SOI semiconductor wafer, active device structures in a thin upper crystalline semiconductor layer being connected with device structures within substrate by means of electrical connections formed through the insulating layer, wherein a sequence of main method steps is performed

in specified areas, performing an ion implantation with highly energetic ions from the front through the single crystalline semiconductor layer and the insulating layer into the substrate;

performing a temperature treatment for activating the implanted ions;

forming upper device structures in the single crystalline layer;

forming vias in the insulating layer at locations where no active thin single crystalline silicon layer is present;

filling the vias in the insulating layer with a metallic material;

forming metallization layers, insulated from each other, within the area of the active device structures and electrically connecting the upper structures with those device structures within the substrate by means of the metal filling in said vias in the insulating layer; and

the metallization layers having metal conductors (15, 15′

), the metal conductors being provided in the form of metal bridges on at least two non-identical levels above the insulating layer.