Multiprotocol RFID reader

• US 7,197,279 B2
• Filed: 12/23/2004
• Issued: 03/27/2007
• Est. Priority Date: 12/31/2003
• Status: Expired due to Fees

• Current Assignee: WJ Communications, Inc. (Qorvo, Inc.)
• Original Assignee: WJ Communications, Inc. (Qorvo, Inc.)
• Inventors: Bellantoni, John Vincent
• Primary Examiner(s): Urban; Edward F.
• Assistant Examiner(s): Jackson; Blane J.
• Application Number:
  US11/021,302
• Publication Number:
  US 20050231367A1
• Time in Patent Office: 824 Days
• Field of Search: 455/347, 455/344, 455/127.1, 455/127.2, 455/108, 455/101, 455/227, 455/272, 455/273, 455/277.1, 455/276.1, 455/280, 455/285, 455/288, 455/323, 455/334, 455/378, 375/320, 375/300, 375/334, 375/303
• US Class Current: 455/41.2
• CPC Class Codes: G06K 19/07741 comprising a first part operating as a regular record carrier and a second attachable part that changes the functional appearance of said record carrier, e.g. a contact-based smart card with an adapter part which, when attached to the contact card makes the contact card function as a non-contact card
• CPC Class Codes: G06K 7/0008 General problems related to the reading of electronic memory record carriers, independent of its reading method, e.g. power transfer
• CPC Class Codes: G06K 7/10128 the step consisting of detection of the presence of one or more record carriers in the vicinity of the interrogation device
• CPC Class Codes: G06K 7/10316 using at least one antenna particularly designed for interrogating the wireless record carriers antennas in general H01Q1/22
• CPC Class Codes: G06K 7/10346 the antenna being of the far field type, e.g. HF types or dipoles

Abstract

An RFID reader accessible thorough a personal computer and includes a PC card interface and a controller both operating according to clock signals from a crystal oscillator. The RFID reader further includes a linearized power amplifier modulator in a transmit path, a receive chain capable of demodulating EPCglobal Class_1 and Class_0 signals from RFID tags, and an integrated switching device for selecting one of a plurality of antenna for transmitting or receiving RF signals.

Claims

1. An RFID reader accessible through a computer system for interrogating at least one RFID tag, comprising:

a frequency synthesizer configured to generate a continuous wave signal;

a controller coupled to the computer system through a PC card interface and configured to generate a plurality of control signals, the controller and the PC card interface both operate based on a clock signal generated by a crystal oscillator that is referenced by the frequency synthesizer in generating the continuous wave signal, and wherein a frequency of the clock signal is about 14.75 MHz or an integer multiple of 14.75 MHz;

a transmit chain configured to form a transmit signal from a first portion of the continuous wave signal according to at least one of the control signals;

a frequency divider coupled between the crystal oscillator and the controller; and

a receive chain configured to form a plurality of signals for extracting information associated with the RFID tag based on a received signal from the RFID tag and a second portion of the continuous wave signal;

wherein the frequency synthesizer, the controller, the transmit chain, and the receive chain are inter-coupled within a housing suitable for plugging in a PCMCIA slot of the computer system.

2. The reader of claim 1 wherein the transmit chain comprises a linearized power amplifier modulator, which comprises:

a ramp generator configured to receive a modulation control signal from the controller and to generate a ramp signal based on the modulation control signal;

a current mirror coupled to the ramp generator and configured to generate a reference current based on the ramp signal; and

a power amplifier receiving the reference current at a bias input and at least a portion of the continuous wave signal at a signal input and configured to output the transmit signal.

3. The reader of claim 2 wherein the control signal comprises step transitions, the ramp signal comprises linear ramps each ramping a corresponding step transition over a ramp time period.

4. The reader of claim 2 wherein the ramp signal is a voltage signal and the reference current is linearly proportional to the ramp signal.

5. The reader of claim 4 further comprising a low-pass filter coupled to the output of the ramp generator and configured to smooth the ramp signal.

6. The reader of claim 1 further comprising a switching device coupled to the transmit chain and configured to connect at least one of a plurality of antennas to the transmit chain based on an antenna select control signal from the controller, the switching device comprising:

first, second, and third filter networks, and

a switch element coupled to the controller and between the first filter network and the second and third filter networks and configured to connect either the second or the third filter network to the first filter network; and

wherein parasitic components associated with the switch element and the first, second and third filter networks are integrated into one low-pass filter prototype structure.

7. The reader of claim 6 wherein the second and third filter networks are substantially matched such that each component in the second filter network matches a corresponding component in the third filter network.

8. The reader of claim 7 wherein the first, second and third filter networks comprise inductors and capacitors, and wherein values of inductors or capacitors in the first, second and third networks are selected to account for values of the parasitic components in the switch element such that the switching device constitutes one low-pass filter prototype structure.

9. The reader of claim 1 wherein the receive chain generates at least one in-phase signal, at least one quadrature signal, and at least one frequency-shift-keying (FSK) signal.

10. The reader of claim 9 wherein the receive chain comprises:

an in-phase demodulator configured to generate the at least one in-phase signal;

a quadrature demodulator configured to generate the at least one quadrature signal;

a image reject mixer (IRM) coupled to the in-phase and quadrature demodulators; and

a frequency shift keying (FSK) receiver coupled to the IRM and configured to generate the at least one FSK signal.

11. The reader of claim 10 wherein the IRM and the in-phase demodulator share a first mixer and the IRM and the quadrature demodulator share a second mixer, the IRM further comprising:

a first all-pass filter coupled to the in-phase demodulator and configured to cause a first phase shift in a first intermediate frequency (IF) signal from the in-phase demodulator;

a second all-pass filter coupled to the quadrature demodulator and configured to cause a second phase shift in a second IF signal from the quadrature demodulator; and

a summer coupled to first and second all-pass filter networks and configured to generate an output that is a sum of the first IF signal from the first all-pass filter and the second IF signal from the second all-pass filter; and

wherein each of the first and second all-pass filters comprises an op-amp with associated components, and wherein component values in the first all-pass filter and the second all-pass filter are selected such that a total relative phase shift between the first IF signal from the first all-pass filter and the second IF signal from the second all-pass filter is 90°

.

12. The reader of claim 11 further comprising a low-pass filter structure wherein the summer is integrated in the low-pass filter structure and shares at least one operational amplifier with the low-pass filter structure.

13. The reader of claim 11 further comprising blocking capacitors inserted at specified locations in the IRM, wherein capacitance values of the blocking capacitors are selected such that the IRM has a high-pass function to filter out frequencies below a predetermined band of IF frequencies.

14. The reader of claim 1 further comprising a power detector and an output power control module, the power detector being coupled to the transmit and receive chains and configured to detect a signal power level in the receive chain and to provide a feedback to the transmit chain, the output power control module being configured to adjust a power level in the transmit signal according to the feedback.

15. The reader of claim 14 wherein the power detector generates an additional signal to indicate a possible antenna fault.

16. An RFID reader capable of interrogating EPCglobal class_—

0 and class_—

1 RFID tags, comprising;

a frequency synthesizer configured to generate a local oscillator signal;

an RF receiver configured to receive the local oscillator signal from the frequency synthesizer and an RF signal from an RFID tag and to generate at least one in-phase signal, at least one quadrature signal, and at least one frequency-shift-keying (FSK) signal based on the RF signal and the local oscillator signal;

wherein the RF receiver further comprises;

an in-phase demodulator configured to generate the at least one in-phase signal;

a quadrature demodulator configured to generate the at least one quadrature signal;

an image reject mixer (IRM) coupled to the in-phase and quadrature demodulators;

a frequency shift keying (FSK) receiver coupled to the IRM and configured to generate the at least one FSK signal; and

an adjustable phase shifter coupled between the frequency synthesizer and in-phase and quadrature demodulators and configured to cause an adjustable phase shift in the local oscillator signal so as to minimize conversion of phase noise in the local oscillator signal into amplitude noise in the in-phase and quadrature signals.

17. The reader of claim 16 wherein the IRM and the in-phase demodulator share a first mixer configured to generate a first intermediate frequency (IF) signal by mixing a first portion of the RF signal with a first portion of the local oscillator signal, and the IRM and the quadrature demodulator share a second mixer configured to generate a second IF signal by mixinga second portion of the RF signal and a phase-shifted second portion of the local oscillator signal, the IRM further comprising:

a first all-pass filter coupled to the in-phase demodulator and configured to cause a first phase shift in the first IF signal from the in-phase demodulator;

a second all-pass filter coupled to the quadrature demodulator and configured to cause a second phase shift in the second IF signal from the quadrature demodulator; and

a summer coupled to first and second all-pass filter networks and configured to generate an output that is a sum of the first IF signal from the first all-pass filter and the second IF signal from the second all-pass filter; and

wherein each of the first and second all-pass filters comprises an op-amp with associated components, and wherein component values in the first and second all-pass filters are selected such that a total relative phase shift between the first IF signal and the second IF signal is 90°

or nearly 90°

.

18. The reader of claim 17 wherein the IRM further comprises a first buffer amplifier coupled between the first mixer and the first all-pass filter and a second buffer amplifier coupled between the second mixer and the second all-pass filter, the first and second buffer amplifiers are substantially identical in configuration.

19. The reader of claim 17 further comprising blocking capacitors placed at specified locations in the IRM, wherein the capacitance values of the blocking capacitors are selected so that the IRM has a high-pass function to filter out frequencies below a predetermined frequency band.

20. The reader of claim 17 wherein the summer includes a first resistor coupled to the first all-pass filter via a first blocking capacitor and a second resistor coupled to the second all-pass filter via a second blocking capacitor wherein values of the first and second resistors and first and second blocking capacitors are selected to compensate for a difference in impedance between the first all-pass filter and the second all-pass filter so that the first IF signal and the second IF signal are equally or nearly equally weighted in the sum generated by the summer.

21. The reader of claim 17 further comprising a low-pass filter structure wherein the low-pass filter structure and the summer are integrated to share at least one operational amplifier.

22. An image reject mixer (IRM) for use with an RF receiver configured to receive a local oscillator signal from a local frequency synthesizer and an RF signal from a remote object, comprising:

a first mixer configured to generate a first intermediate frequency (IF) signal by mixing a first portion of the RF signal with a first portion of the local oscillator signal,

a second mixer configured to generate a second IF signal by mixing a second portion of the RF signal and a phase-shifted second portion of the local oscillator signal;

a first all-pass filter coupled to the first mixer and configured to cause a first phase shift in the first IF signal from the in-phase demodulator;

a second all-pass filter coupled to the second mixer and configured to cause a second phase shift in the second IF signal from the quadrature demodulator; and

a summer coupled to first and second all-pass filter networks and configured to generate an output that is a sum of the first IF signal from the first all-pass filter and the second IF signal from the second all-pass filter;

blocking capacitors placed at specified locations in the IRM, wherein the capacitance values of the blocking capacitors are selected so that the IRM has a high-pass function to filter out frequencies below a predetermined frequency band; and

wherein each of the first and second all-pass filters comprises an op-amp with associated components, and wherein component values in the first and second all-pass filters are selected such that a total relative phase shift between the first IF signal and the second IF signal is 90°

or nearly 90°

.

23. The IRM of claim 22 wherein the IRM further comprises a first buffer amplifier coupled between the first mixer and the first all-pass filter and a second buffer amplifier coupled between the second mixer and the second all-pass filter, the first and second buffer amplifiers are substantially identical in configuration.

24. The IRM of claim 22 wherein the summer includes a first resistor coupled to the first all-pass filter via a first blocking capacitor and a second resistor coupled to the second all-pass filter via a second blocking capacitor wherein values of the first and second resistors and first and second blocking capacitors are selected to compensate for a difference in impedance between the first all-pass filter and the second all-pass filter so that the first IF signal and the second IF signal are equally or nearly equally weighted in the sum generated by the summer.

25. The IRM of claim 22 further comprising a low-pass filter structure wherein the summer are integrated in the low-pass filter structure and shares at least one operational amplifier with the low-pass filter structure.

26. A method for interrogating an RFID tag, comprising:

generating a clock signal;

generating a continuous wave signal referencing the clock signal;

generating a plurality of control signals;

controlling the generation of the control signals via a PC card interface operating based on the clock signal;

modulating the continuous wave signal according to one of the plurality of control signals;

receiving an RF signal from the RFID tag;

demodulating the RF signal by mixing it with a portion of the continuous wave signal to generate at least one in-phase signal, at least one quadrature signal, and at least one FSK signal;

selecting the at least one in-phase signal, the at least one quadrature signal, or the at least one FSK signal to draw information included in the RF signal from the RFID tag; and

causing an adjustable phase shift in the portion of the continuous wave signal to minimize conversion of phase noise in the continuous wave signal into amplitude noise in the at least one in-phase signal, at least one quadrature signal, and at least one FSK signal.

27. The method of claim 26, further comprising:

generating a ramp signal according to one of the control signals comprising step transitions, the ramp signal comprising linear ramps each corresponding to a step transition in the control signal;

generating a reference current signal according to the ramp signal using a current mirror;

supplying the reference current signal to a power amplifier receiving a portion of the continuous wave signal; and

modulating the continuous wave signal according to the reference current signal using the power amplifier.

28. The method of claim 27 wherein the reference current signal is linearly proportional to the ramp signal.