Method and apparatus for reducing interference

  • US 7,199,650 B1
  • Filed: 06/29/2005
  • Issued: 04/03/2007
  • Est. Priority Date: 10/11/2000
  • Status: Expired due to Term
First Claim
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1. A method of reducing interference present in a circuit, the method comprising:

  • providing a first block of digital circuitry connected to a second block of digital circuitry by a signal line; and

    inserting buffer circuitry between the first and second blocks of digital circuitry for containing high frequency current within the first block of digital circuitry by providing a path for high frequency current to flow to ground, while allowing low frequency signals to pass through the signal line, wherein the buffer circuitry is comprised of one or more inverters, and wherein at least one of the inverters is powered by a filtering capacitor coupled to the one or more inverter.

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