Interleaving apparatus and method for symbol mapping in an HSDPA mobile communication system

• US 7,200,792 B2
• Filed: 12/20/2002
• Issued: 04/03/2007
• Est. Priority Date: 12/21/2001
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Noh-Sun, Moon, Yong-Suk, Kim, Hun-Kee, Yoon, Jae-Seung, Lee, Jun-Sung, Choi, Gin-Kyu
• Primary Examiner(s): CHUNG, PHUNG M
• Application Number:
  US10/324,215
• Publication Number:
  US 20030120995A1
• Time in Patent Office: 1,565 Days
• Field of Search: None
• US Class Current: 714/755
• CPC Class Codes: H03M 13/258 with turbo codes, e.g. Turbo Trellis Coded Modulation [TTCM]
• CPC Class Codes: H03M 13/271 Row-column interleaver with permutations, e.g. block interleaving with inter-row, inter-column, intra-row or intra-column permutations
• CPC Class Codes: H03M 13/2771 Internal interleaver for turbo codes H03M13/2714 and H03M13/2725 take precedence
• CPC Class Codes: H03M 13/2957 Turbo codes and decoding
• CPC Class Codes: H03M 13/356 Unequal error protection [UEP]
• CPC Class Codes: H04L 1/0043 Realisations of complexity reduction techniques, e.g. use of look-up tables
• CPC Class Codes: H04L 1/0071 Use of interleaving interleaving per se H03M13/27
• CPC Class Codes: H04L 2001/0098 Unequal error protection

Abstract

In an apparatus for data transmission in a communication system, a turbo encoder encodes data bits to generate systematic bits and parity bits, and a rate matcher matches the systematic bits and parity bits. A first interleaver writes the rate-matched systematic bits on a row by row basis, and performs inter-column permutation. A second interleaver writes the rate-matched parity bits on a row-by-row basis, and performs inter-column permutation. A modulator alternatively collects the permutated bits on a column by column basis from the first and second interleavers, and maps collected bits from the first and second interleavers onto one modulation symbol, wherein a size of the first interleaver is equal to a size of the second interleaver.

Claims

1. An apparatus for data transmission in a communication system, comprising:

a turbo encoder for coding data bits to generate systematic bits and parity bits;

a rate matcher for rate matching the systematic bits and parity bits;

a first interleaver for writing the rate-matched systematic bits on a row by row basis, and performing inter-column permutation;

a second interleaver for writing the rate-matched parity bits on a row-by-row basis, and performing inter-column permutation;

a modulator for alternatively collecting the permutated bits on a column by column basis from the first interleaver and the second interleaver, and mapping collected bits from the first interleaver and second interleaver onto one modulation symbol,

wherein a size of the first interleaver is equal to a size of the second interleaver.

2. The apparatus of claim 1, wherein if a number of the rate-matched systematic bits is less than a number of the rate-matched parity bits, part of the rate-matched parity bits is written next to the rate-matched systematic bits in the first interleaver.

3. The apparatus of claim 1, wherein if a number of the rate-matched systematic bits is greater than a number of the rate-matched parity bits, part of the rate-matched systematic bits is written prior to the rate-matched parity bits in the second interleaver.

4. The apparatus of claim 1, wherein if the modulation scheme is 16QAM (16-ary Quadrature Amplitude Modulation), alternatively outputting 2 bits on a column by column basis from the first interleaver and second interleaver.

5. The apparatus of claim 1, wherein if the modulation scheme is 16QAM (16-ary Quadrature Amplitude Modulation), mapping onto one modulation symbol 2 bits from the first interleaver and 2 bits from the second interleaver.

6. A method for data transmission in a communication system, comprising the steps of:

turbo coding data bits to generate systematic bits and parity bits;

rate matching the systematic bits and parity bits;

writing the rate-matched systematic bits on a row by row basis in a first interleaver and the rate-matched parity bits on a row by row basis in a second interleaver;

performing inter-column permutation in the first interleaver and in the second interleaver;

alternatively collecting the permutated bits on a column by column basis from the first interleaver and the second interleaver;

mapping the collected bits from the first interleaver and second interleaver onto one modulation symbol,

wherein a size of the first interleaver is equal to a size of the second interleaver.

7. The method of claim 6, wherein if a number of the rate-matched systematic bits is less than a number of the rate-matched parity bits, part of the rate-matched parity bits is written next to the rate-matched systematic bits in the first interleaver.

8. The method of claim 6, wherein if a number of the rate-matched systematic bits is greater than a number of the rate-matched parity bits, part of the rate-matched systematic bits is written prior to the rate-matched parity bits in the second interleaver.

9. The method of claim 6, wherein if the modulation scheme is 16QAM (16-ary Quadrature Amplitude Modulation), alternatively outputting 2 bits on a column by column basis from the first interleaver and second interleaver.

10. The method of claim 6, wherein if the modulation scheme is 16QAM (16-ary Quadrature Amplitude Modulation), mapping onto one modulation symbol 2 bits from the first interleaver and 2 bits from the second interleaver.

11. An apparatus for receiving data in a communication system, comprising:

a demodulator for demodulating a received symbol into a plurality of systematic bits and parity bits;

a first deinterleaver for writing the plurality of systematic bits on a column by column basis and performing inter-column permutation;

a second deinterleaver for writing the plurality of parity bits on a column by column basis and performing inter-column permutation;

a rate matcher for rate matching the de-interleaved systematic bits and parity bits; and

a decoder for decoding the rate matched systematic bits and parity bits,

wherein a size of the first deinterleaver is equal to a size of the second deinterleaver.

12. The apparatus of claim 11, wherein if a number of the systematic bits is less than a number of the parity bits, part of the parity bits is written next to systematic bits in the first deinterleaver.

13. The apparatus of claim 11, wherein if a number of the systematic bits is greater than a number of the parity bits, part of the systematic bits is written prior to the parity bits in the second deinterleaver.

14. A method for receiving data in a communication system, comprising:

demodulating a received symbol into a plurality of systematic bits and parity bits;

writing the plurality of systematic bits on a column by column basis in a first deinterleaver and performing inter-column permutation, and writing the plurality of parity bits on a column by column basis in a second deinterleaver and performing inter-column permutation;

rate marching the de-interleaved systematic bits and parity bits; and

decoding the rate matched systematic bits and parity bits,

wherein a size of the first deinterleaver is equal to a size of the second deinterleaver.

15. The method of claim 14, wherein if a number of the systematic bits is less than a number of the parity bits, part of the parity bits is written next to the systematic bits in the first deinterleaver.

16. The method of claim 14, wherein if a number of the systematic bits is greater than a number of the parity bits, part of the systematic bits is written prior to the parity bits in the second deinterleaver.