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Voltage tolerant input buffer

  • US 7,202,699 B1
  • Filed: 09/13/2004
  • Issued: 04/10/2007
  • Est. Priority Date: 09/15/2003
  • Status: Active Grant
First Claim
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1. A buffer circuit comprising:

  • a differential circuit, the differential circuit comprising a first differential transistor pair and a second differential transistor pair, the first differential transistor pair and the second differential transistor pair being complementary; and

    a plurality of switches coupled with the differential circuit;

    wherein the plurality of switches apply a voltage to the differential circuit in a first state and isolate the differential circuit from the voltage in a second state, the voltage being at a higher potential in the second state than in the first state, and wherein the buffer circuit is to operate in both the first state and the second state.

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