Apparatus and method for parallel and serial PCI hot plug signals

• US 7,203,785 B2
• Filed: 08/31/2004
• Issued: 04/10/2007
• Est. Priority Date: 03/30/2001
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Bennett, Joseph A., Sastry, David
• Primary Examiner(s): Dang; Khanh
• Application Number:
  US10/930,112
• Publication Number:
  US 20050235078A1
• Time in Patent Office: 952 Days
• Field of Search: 710/71, 710/8, 710/11, 710/104, 710/302
• US Class Current: 710/302
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 13/4081 Live connection to bus, e.g. hot-plugging current or voltage limitation during live insertion H02H9/004
• CPC Class Codes: G06F 2213/0024 Peripheral component interconnect [PCI]

Abstract

A method and apparatus are provided for operating a hot plug system. A first device may determine whether the system is to operate in one of a parallel mode or a serial mode. A second device may control a mode of the chipset based on the determination of the first device. The second device may include logic, a first multiplexer, a second multiplexer, a first converter and a second converter all provided on the chipset.

Claims

1. A circuit for a protocol having at least first and second different modes, comprising:

first interface logic for one of the modes;

a single set of I/O pins to transfer signals in either of the modes to external devices, at least some of the same pins changing their function in different ones of the modes;

converters to convert the modes to each other;

multiplexers to selectively couple the pins to the first interface logic either directly or through the converters;

second interface logic for the other of the modes, the second interface logic being adapted to produce a signal to control the selective coupling.

2. The circuit of claim 1 where the first and second modes comprise a parallel mode and a serial mode.

3. The circuit of claim 2 where the first interface logic implements the parallel mode.

4. The circuit of claim 2 where the protocol is a PCI protocol.

5. The circuit of claim 1 where one of the interface logics determines which of the modes is to be implemented.

6. The circuit of claim 5 where the one interface logic is the first interface logic.

7. The circuit of claim 6 where the second interface logic controls the selective coupling in response to which of the modes is to be implemented.

8. The circuit of claim 1 where the circuit is fabricated in a chipset.

9. The circuit of claim 8 where the protocol is a PCI protocol.

10. A system, comprising:

a processor;

a bus coupled to the processor;

a circuit coupled to the bus to transfer data to and from the bus according to a protocol that has both parallel and serial modes, the circuit comprising

first interface logic for one of the modes;

a single set of I/O pins for transferring signals in either of the modes to external devices, at least some of the same pins changing their function in different ones of the modes;

converters for converting the modes to each other;

multiplexers for selectively coupling the pins to the first interface logic either directly or through the converters;

second interface logic for the other of the modes, the second interface logic being adapted to produce a signal to control the selective coupling.

11. The system of claim 10 further comprising a memory control hub coupled between the circuit and the bus.

12. The system of claim 11 further comprising RAM memory coupled to the memory control hub.

13. The system of claim 10 where the protocol is a PCI protocol.

14. The system of claim 13 further comprising a one or more PCI-protocol devices coupled to the pins.

15. The system of claim 10 where the circuit is fabricated in a chipset.

16. A method, comprising:

convening signals in a first-mode to a second mode of the same designated protocol;

producing a control signal in the second mode of the designated protocol;

selectively coupling the signals in either the first mode or the second mode to a set of I/O pins in response to the control signal.

17. The method of claim 16 where the first and second modes comprise a parallel mode and a serial mode.

18. The method of claim 16 where the designated protocol is a PCI protocol.

19. The method of claim 16 where at least one of the I/O pins having a first function if coupled to the signals in the first mode, has a different function if coupled to the signals in the second mode.