Driver for switching circuit and drive method

• US 7,205,821 B2
• Filed: 11/19/2003
• Issued: 04/17/2007
• Est. Priority Date: 11/29/2002
• Status: Expired due to Fees

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Rutter, Philip
• Primary Examiner(s): Patel; Rajnikant B.
• Application Number:
  US10/536,247
• Publication Number:
  US 20060038545A1
• Time in Patent Office: 1,245 Days
• Field of Search: 363/21.06, 363/89, 363/20, 363/21.01, 363/44, 363/52, 363/84, 363 56- 58, 363/132, 327/427, 327/436, 327/104, 327/108, 307/254, 307/262, 307/571, 307/572
• US Class Current: 327/427
• CPC Class Codes: H02M 1/38 Means for preventing simultaneous conduction of switches
• CPC Class Codes: H02M 3/1588 comprising at least one synchronous rectifier element H02M3/1582, H02M3/1584 take precedence
• CPC Class Codes: H03K 17/04123 in field-effect transistor switches
• CPC Class Codes: H03K 17/04206 in field-effect transistor switches
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

A driver circuit includes monitoring circuitry (32, 34, 36) for monitoring the states of high and low side switches (6, 8). The driver circuit has an adjustable delay for turning on the transistors (6, 8). The delay is decreased when the monitoring circuit detects that a voltage corresponding to one transistor passes a predetermined voltage V1 before a voltage corresponding to the other transistor passes another predetermined point V2, and vice versa.

Claims

1. A drive circuit for a switching circuit, comprising:

first and second gate control outputs for connection to gates of respective first and second insulated gate transistors;

first and second gate drivers connected to the first and second gate control outputs respectively for driving the respective gates to switch the first and second insulated gate transistors on and off alternately;

monitoring circuitry for monitoring voltages on first and second monitor points and hence a state of the first and second insulated gate transistors respectively, the first monitor point being one of the gate of the first insulated gate transistor and a switch node between first and second insulated gate transistors and the second monitor point being the gate of the second insulated gate transistor;

wherein the drive circuit is arranged;

to drive the second gate driver to switch off the second insulated gate transistor and then after a first controllable delay to drive the first gate driver to switch on the first insulated gate transistor;

to compare a first time that the voltage on the first monitor point passes a first predetermined voltage and a second time that the voltage on the second monitor point passes a second predetermined voltage; and

to decrease the first controllable delay if the second time is before the first time and to increase the first controllable delay if the second time is after the first time.

2. A drive circuit according to claim 1 wherein the first monitor point is the first gate control output and the second monitor point is the second gate control output.

3. A drive circuit according to claim 1 wherein the first and second insulated gate transistors are connected together in series at a switch node and the first monitor point is the switch node.

4. A drive circuit according to any preceding claim wherein every time the first controllable delay is increased or decreased the first controllable delay is increased or decreased by a constant predetermined time.

5. A drive circuit according to claim 4 wherein the predetermined time is in the range 1 ns to 5 ns.

6. A drive circuit according to claim 1 wherein the drive circuit is arranged:

to switch off the first insulated gate transistor and after a second controllable delay to switch on the second insulated gate transistor;

to compare a third time that the voltage on the first monitor point passes a third predetermined voltage and a fourth time that the voltage on the second monitor point passes a fourth predetermined voltage; and

to decrease the second controllable delay if the fourth time is after the third time and to increase the second delay E if the fourth time is before the third time, so that the drive circuit can set the first controllable delay to be different from the second controllable delay.

7. A drive circuit according to claim 6 wherein the predetermined voltages are within 1V of a threshold voltage of one of the insulated gate transistors.

8. A switching converter circuit, comprising:

control and sync insulated gate transistors each having a gate, a source and a drain, the control and sync insulated gate transistors being connected together in series at a switch node for driving a load; and

a drive circuit connected to the gates of the control and sync insulated gate transistors for switching the control and sync insulated gate transistors on and off alternately;

wherein the drive circuit is arranged;

to switch off the sync insulated gate transistor and switch on the control insulated gate transistor after a delay;

to monitor voltages at first and second monitoring points, the first monitor point being the switch node or the gate of the control transistor and the second monitor point being the gate of the sync transistor;

to compare the a first time that the voltage en at the first monitoring point rises above a first predetermined voltage and a second time that the voltage at the second monitoring point falls below a second predetermined voltage; and

to decrease the delay if the second time is before the first time and to increase the delay if the second time is after the first time.

9. A method of driving a converter circuit having first and second insulated gate transistors each having, a gate, a source and a drain, the method including the steps of:

(a) switching off the first insulated gate transistor;

(b) switching on the second insulated gate transistor after a first a delay;

(c) monitoring voltages at first and second monitor points, the first monitor points being one of the gate of the first insulated gate transistor and a switch node that is between first and second insulated gate transistors, and the second monitor point being the gate of the second insulated gate transistor; and

(d) comparing a first time that the voltage at the first monitor point passes a first predetermined voltage and a second time that the voltage at the second monitor point passes above a second predetermined voltage;

(e) decreasing the first delay if the second time is after the first time and increasing the first delay if the second time is before the first time; and

(f) switching on the first and second transistors alternately, repeating steps (a) to (c) above when switching on the second transistor and switching off the first transistor.

10. A method according to claim 9 further comprising:

(g) switching off the second insulated gate transistor and switching on the first insulated gate transistor after a second delay;

(h) monitoring the voltages at the first and second monitor points;

(i) comparing a third time that the voltage at the second monitor point falls below a third predetermined voltage and a fourth time that the voltage at the first monitor point rises above a fourth predetermined voltage;

(j) decreasing the second delay if the fourth time is after the third time and increasing the second delay if the fourth time is before the third time; and

repeating steps (g) to (j) above when switching on the first insulated gate transistor and switching off the second insulated gate transistor as the first and second insulated gate transistors are switched on alternately.

11. A method according to claim 9 or 10 wherein the first delay and the second delay are increased or decreased by a predetermined amount in the range 1 ns to 5 ns on each cycle.

12. A method according to claim 9 or 10 wherein the first monitor point is the gate of the first insulated gate transistor.

13. A method according to claim 9 or 10 wherein the first and second insulated gate transistors are connected together in series and have a switch node therebetween for connection to a load, and in which the first monitor point is the switch node.