Shared memory multiprocessor system

• US 7,206,818 B2
• Filed: 08/04/2003
• Issued: 04/17/2007
• Est. Priority Date: 08/20/1998
• Status: Expired due to Fees

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Hamanaka, Naoki, Irie, Naohiko, Okochi, Toshio, Akashi, Hideya, Shonai, Toru
• Primary Examiner(s): Winder; Patrice
• Assistant Examiner(s): Mirza; Adnan M.
• Application Number:
  US10/632,856
• Publication Number:
  US 20040024839A1
• Time in Patent Office: 1,352 Days
• Field of Search: 709/212, 709/215, 709/223
• US Class Current: 709/212
• CPC Class Codes: G06F 15/167 using a common memory, e.g. mailbox
• CPC Class Codes: G06F 2212/682 Multiprocessor TLB consistency

Abstract

Multiprocessor system, having a translation lookaside buffer (TLB) in each processor, and having a structure for avoiding TLB purge overhead. Each processor node is provided with a partial main memory and a physical page map table (PPT). The PPT stores mapping between physical page number of main memory and virtual page number. Every memory access transaction for other node specifies physical address and virtual page number. Instead of strictly maintaining TLB coherency by broadcasting TLB purge transaction, an access destination node checks the coincidence between the virtual page number specified in the memory access transaction and the virtual page number mapped in the PPT when the transaction is received. If both are coincident, the memory access is executed. If not coincident, an error message is transferred to an access requesting source.

Claims

1. A multiprocessor system having a plurality of nodes, each node including at least one CPU, at least one Translation Lookaside Buffer (TLB), each associated with a respective Central Processing Unit (CPU), and a local main memory forming a part of a main memory space of the multiprocessor system, and an inter-node network, each of the nodes further comprising:

a map table having entries corresponding to respective physical pages of said local main memory and storing correspondence between each physical page number of said physical pages and a virtual page number actually mapped to each physical page number;

network transaction generating means for generating, when a result of an address translation using a TLB indicates that a memory access request from a CPU is to be directed to a local main memory of another node, a network transaction corresponding to said memory access request which includes a physical address to be accessed obtained from said result of the address translation using the TLB and a virtual page number designated in said memory access request from the CPU;

transaction receiving means for receiving network transactions transferred from other nodes;

checking means for checking for coincidence between a first virtual page number which is included in a received network transaction and a second virtual page number obtained through reference to said map table using a physical address included in the received memory access transaction and outputting a notice indicating whether said first and second virtual page numbers are coincident; and

main memory access means for executing an access to said local main memory corresponding to said received network transaction when said notice indicates said first and second virtual page numbers are coincident,

wherein when said notice indicates said first and second virtual page numbers are not coincident, an occurrence of an error is informed to the CPU or the CPU of another node if the received network transaction is from said another node.

2. A multiprocessor system according to claim 1, wherein said map table stores a plurality of virtual pages mapped to a physical page.

3. A multiprocessor system according to claim 1, wherein said map table further stores information indicating whether the mapping between a virtual page and a physical page is valid or not.

4. A multiprocessor system according to claim 1, wherein said map table is mapped to a part of a memory space of said multiprocessor system.

5. A multiprocessor system according to claim 1, wherein each node further includes means for selecting physical page numbers in said map table in which a mapped virtual page is stored, among all physical pages of said main memory.

6. A multiprocessor system having a plurality of nodes, each node including at least one Central Processing Unit (CPU) at least one Translation Lookaside Buffer (TLB), each associated with a respective CPU, and a local main memory forming a part of a main memory space of the multiprocessor system, and an inter-node network, each of the nodes further comprising:

a map table having entries corresponding to respective physical pages of said local main memory and storing correspondence between each physical page number of said physical pages and a virtual page number actually mapped to said each physical page number;

network transaction generating means for generating, when a result of an address translation using a TLB indicates that a memory access request from a CPU is to be directed to a local main memory of another node, a network transaction corresponding to said memory access request which includes a physical address to be accessed obtained from said result of the address translation using the TLB and a virtual page number designated in said memory access request from the CPU;

transaction receiving means for receiving network transactions transferred from other nodes;

checking means for checking for coincidence between a first virtual page number which is included in a received network transaction and a second virtual page number obtained through reference to said map table using a physical address included in the received memory access transaction and outputting a notice indicating whether said first and second virtual page numbers are coincident;

main memory access means for executing an access to said local main memory corresponding to said received network transaction when said notice indicates said first and second virtual page numbers are coincident; and

error message generating means for informing a source of said received network transaction of an error when said first and second virtual pages are not coincident,

wherein when said notice indicates said first and second virtual page numbers are not coincident, the occurrence of an error is informed to the CPU or the CPU of another node if the received network transaction is from said another node.

7. A multiprocessor system according to claim 6, wherein said map table stores a plurality of virtual pages mapped to a physical page.

8. A multiprocessor system according to claim 6, wherein said map table further stores information indicating whether the mapping between a virtual page and a physical page is valid or not.

9. A multiprocessor system according to claim 6, wherein said map table is mapped to a part of a memory space of said multiprocessor system.

10. A multiprocessor system according to claim 6, wherein each node further includes means for selecting physical page numbers in said map table in which a mapped virtual page is stored, among all physical pages of said main memory.