Method and structures for testing a semiconductor wafer prior to performing a flip chip bumping process

  • US 7,221,173 B2
  • Filed: 09/29/2004
  • Issued: 05/22/2007
  • Est. Priority Date: 09/29/2004
  • Status: Active Grant
First Claim
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1. An interface assembly for a semiconductor wafer, said interface assembly comprising:

  • a flip chip bonding pad including a region for performing a bumping process; and

    a test pad integrally constructed with said bonding pad that form an integral conductive structure such that separate interconnect testing lines from said test pad to said bonding pad are not present in said integral structure, said test pad being coplanar relative to said flip chip bonding pad and including a probe region for performing wafer-level testing prior to performing said bumping process.

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