Programmable processor and method for matched aligned and unaligned storage instructions

  • US 7,222,225 B2
  • Filed: 11/20/2003
  • Issued: 05/22/2007
  • Est. Priority Date: 08/16/1995
  • Status: Expired due to Fees
First Claim
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1. A programmable processor comprising:

  • a data path;

    an external interface operable to receive data from an external source and communicate the received data over the data path;

    a cache operable to retain data communicated between the external interface and the data path;

    a register file coupled to the data path and containing a plurality of registers; and

    an execution unit coupled to the data path, the execution unit configurable to perform a group instruction that operates on a plurality of data elements in partitioned fields of a register to produce a catenated result, the execution unit further configurable to execute;

    (i) an aligned instruction operable to copy first data according to an aligned memory address, the first data having a data width, the data width specified as a fixed value by the aligned instruction, the aligned memory address being one of a plurality of memory addresses regularly spaced at alignment boundaries separated by the data width; and

    (ii) an unaligned instruction operable to copy second data according to an unaligned memory address, the second data having the data width, the data width specified as a fixed value by the unaligned instruction, the second data being permitted to cross an alignment boundary of the data width, the unaligned memory address being a memory address that is not constrained to be one of the plurality of memory addresses regularly spaced at alignment boundaries separated by the data width.

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