Programmable processor and method for matched aligned and unaligned storage instructions

• US 7,222,225 B2
• Filed: 11/20/2003
• Issued: 05/22/2007
• Est. Priority Date: 08/16/1995
• Status: Expired due to Fees

• Current Assignee: Microunity Systems Engineering Incorporated
• Original Assignee: Microunity Systems Engineering Incorporated
• Inventors: Moussouris, John, Hansen, Craig
• Primary Examiner(s): Coleman; Eric
• Application Number:
  US10/716,561
• Publication Number:
  US 20040156248A1
• Time in Patent Office: 1,279 Days
• Field of Search: 712/204, 712/22
• US Class Current: 712/204
• CPC Class Codes: G06F 15/7832 on one IC chip (single chip microprocessors)
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/30018 Bit or string instructions
• CPC Class Codes: G06F 9/30025 Format conversion instructions, e.g. Floating-Point to Integer, decimal conversion
• CPC Class Codes: G06F 9/30029 Logical and Boolean instructions, e.g. XOR, NOT
• CPC Class Codes: G06F 9/30032 Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/30054 Unconditional branch instructions
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/30109 having multiple operands in a single register
• CPC Class Codes: G06F 9/30112 comprising data of variable length
• CPC Class Codes: G06F 9/3012 Organisation of register space, e.g. banked or distributed register file
• CPC Class Codes: G06F 9/30123 according to context, e.g. thread buffers
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/3016 Decoding the operand specifier, e.g. specifier format
• CPC Class Codes: G06F 9/30167 of immediate specifier, e.g. constants
• CPC Class Codes: G06F 9/3816 Instruction alignment, e.g. cache line crossing
• CPC Class Codes: G06F 9/3824 : Operand accessing
• CPC Class Codes: G06F 9/383 : Operand prefetching cache prefetching G06F12/0862
• CPC Class Codes: G06F 9/3851 : from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3861 : Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00
• CPC Class Codes: G06F 9/3873 : Variable length pipelines, e.g. elastic pipeline
• CPC Class Codes: G06F 9/3885 : using a plurality of independent parallel functional units

Abstract

A programmable processor and method for improving the performance of processors by incorporating an execution unit operable to decode and execute single instructions in an instruction set comprising (a) group instructions that operate on a plurality of data elements in partitioned fields of a register to produce a catenated result, (b) aligned memory operations that move data between memory and register where the memory operand is aligned, and (c) unaligned memory operations where the memory operand is unaligned.

Claims

1. A programmable processor comprising:

a data path;

an external interface operable to receive data from an external source and communicate the received data over the data path;

a cache operable to retain data communicated between the external interface and the data path;

a register file coupled to the data path and containing a plurality of registers; and

an execution unit coupled to the data path, the execution unit configurable to perform a group instruction that operates on a plurality of data elements in partitioned fields of a register to produce a catenated result, the execution unit further configurable to execute;

(i) an aligned instruction operable to copy first data according to an aligned memory address, the first data having a data width, the data width specified as a fixed value by the aligned instruction, the aligned memory address being one of a plurality of memory addresses regularly spaced at alignment boundaries separated by the data width; and

(ii) an unaligned instruction operable to copy second data according to an unaligned memory address, the second data having the data width, the data width specified as a fixed value by the unaligned instruction, the second data being permitted to cross an alignment boundary of the data width, the unaligned memory address being a memory address that is not constrained to be one of the plurality of memory addresses regularly spaced at alignment boundaries separated by the data width.

2. The processor of claim 1 wherein the aligned instruction comprises a load instruction operable to copy the first data from memory at the aligned memory address to a register, and the unaligned instruction comprises a load instruction operable to copy the second data from memory at the unaligned memory address to a register.

3. The processor of claim 1 wherein the aligned instruction comprises a store instruction operable to copy the first data from a register to memory at the aligned memory address, and the unaligned instruction comprises a store instruction operable to copy the second data from a register to memory at the unaligned memory address.

4. The processor of claim 1 wherein the group instruction is capable of operating on data having a data width of 128 bits.

5. The processor of claim 1 wherein the group instruction is a group floating-point instruction.

6. The processor of claim 1 wherein the group instruction is a group integer instruction.

7. The processor of claim 1 wherein the aligned instruction and the unaligned instruction are capable of accessing the first data and the second data, each having the data width of 128 bits.

8. The processor of claim 1 wherein the aligned instruction and the unaligned instruction are capable of accessing the first data and the second data, each having the data width of 64 bits.

9. The processor of claim 1 wherein the plurality of regularly spaced memory addresses are separated by intervals of 128 bits.

10. The processor of claim 1 wherein the plurality of regularly spaced memory addresses are separated by intervals of 64 bits.

11. The processor of claim 1 wherein the aligned instruction responds by generating an exception if the aligned memory address is not one of a plurality of memory addresses regularly spaced at alignment boundaries separated by the data width.

12. The processor of claim 1 wherein the execution unit is further configurable to execute two aligned instructions in parallel using hardware capable of executing a single unaligned instruction.

13. The processor of claim 1 wherein the aligned instruction corresponds to a first binary code and the unaligned instruction corresponds to a second binary code, the first binary code matching the second binary code in all but one bit position.

14. A method of providing data and memory capabilities in a programmable processor, the method comprising:

providing, in an instruction set for the processor, a group instruction that operates on a plurality of data elements in partitioned fields of at least one register to produce a catenated result;

providing, in the instruction set for the processor, an aligned instruction operable to copy first data according to an aligned memory address, the first data having a data width, the data width specified as a fixed value by the aligned instruction, the aligned memory address being one of a plurality of memory addresses regularly spaced by the data width; and

providing, in the instruction set for the processor, an unaligned instruction operable to copy second data according to an unaligned memory address, the second data having the data width, the data width specified as a fixed value by the unaligned instruction, the unaligned memory address being a memory address that is not constrained to be one of the plurality of memory addresses regularly spaced by the data width.

15. The method of claim 14 wherein the aligned instruction comprises a load instruction operable to copy the first data from memory at the aligned memory address to a register, and the unaligned instruction comprises a load instruction operable to copy the second data from memory at the unaligned memory address to a register.

16. The method of claim 14 wherein the aligned instruction comprises a store instruction operable to copy the first data from a register to memory at the aligned memory address, and the unaligned instruction comprises a store instruction operable to copy the second data from a register to memory at the unaligned memory address.

17. The method of claim 14 wherein the group instruction is capable of operating on data having a data width of 128 bits.

18. The method of claim 14 wherein the group instruction is a group floating-point instruction.

19. The method of claim 14 wherein the group instruction is a group integer instruction.

20. The method of claim 14 wherein the aligned instruction and the unaligned instruction are capable of accessing the first data and the second data, each having the data width of 128 bits.

21. The method of claim 14 wherein the aligned instruction and the unaligned instruction are capable of accessing the first data and the second data, each having the data width of 64 bits.

22. The method of claim 14 wherein the plurality of regularly spaced memory addresses are separated by intervals of 128 bits.

23. The method of claim 14 wherein the plurality of regularly spaced memory addresses are separated by intervals of 64 bits.

24. The method of claim 14 wherein the aligned instruction responds by generating an exception if the aligned memory address is not one of a plurality of memory addresses regularly spaced at alignment boundaries separated by the data width.

25. The method of claim 14 wherein two aligned instructions are capable of parallel execution.

26. The method of claim 14 wherein the aligned instruction corresponds to a first binary code and the unaligned instruction corresponds to a second binary code, the first binary code matching the second binary code in all but one bit position.