High bandwidth reconfigurable on-chip network for reconfigurable systems

• US 7,224,184 B1
• Filed: 11/05/2004
• Issued: 05/29/2007
• Est. Priority Date: 11/05/2004
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Becker, Tobias J., Levi, Delon
• Primary Examiner(s): Tran; Anh Q.
• Application Number:
  US10/981,932
• Time in Patent Office: 935 Days
• Field of Search: 326 37- 41, 326/47
• US Class Current: 326/41
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17752 for hot reconfiguration
• CPC Class Codes: H03K 19/17756 for partial configuration or partial reconfiguration

Abstract

A crossbar switch (50) is implemented in a reconfigurable circuit, such as a FPGA, instantiated with a number of modules (40), the crossbar switch (50) providing communication links between the modules (40). The modules (40) and crossbar switch (50) can be easily updated in a partial reconfiguration process changing only portions of modules (40) and the crossbar switch (50) while other portions remain active. The crossbar switch (50) uses individual wiring to independently connect module outputs and inputs so that asynchronous communications can be used. The crossbar switch (50) can be implemented in different embodiments including a Clos crossbar switch, and a crossbar switch connecting each module output only to a corresponding module input, allowing for a reduction in the amount of FPGA resources required to create the crossbar switches.

Claims

1. A programmable logic device (PLD) comprising:

modules for implementing tasks, the modules being reconfigurable; and

a crossbar switch providing communication paths between the modules, the crossbar switch being dynamically reconfigurable while communication occurs over a portion of the crossbar switch between modules.

2. The PLD of claim 1, wherein the crossbar switch provides a connection from each module output to select inputs of other modules, the select inputs of each module being less than the total inputs of the module.

3. The PLD of claim 1, wherein the crossbar switch provides a connection from each module input to each module output.

4. The PLD of claim 1, wherein signals provided on the communications paths through the crossbar switch operate asynchronously.

7. The PLD of claim 1, wherein the crossbar switch comprises a Clos crossbar switch.

8. The PLD of claim 1 comprising a series of multiplexers provided in a channel between outputs and inputs of the modules, wherein the multiplexers are formed using IMUXs of CLBs.

9. The PLD of claim 8, wherein the dynamic reconfiguration of the crossbar switch is performed by programming a configuration memory array cell to change select inputs of the IMUXs.

10. The PLD of claim 9, wherein the dynamic reconfiguration comprises partial reconfiguration.

11. The PLD of claim 10, wherein the crossbar switch provides a connection from each output of a portion of the modules only to corresponding inputs of another portion of the modules.

12. The PLD of claim 1, wherein the crossbar switch provides a connection from each output of a portion of the modules only to corresponding inputs of another portion of the modules.

5. A programmable logic device (PLD) comprising:

modules for implementing tasks, the modules being reconfigurable; and

a crossbar switch providing communication paths between the modules, the crossbar switch being reconfigurable, wherein flip-flops are provided only before a first multiplexer and after a last multiplexer in a channel to provide for synchronous operation.

6. The PLD of claim 5, wherein communication paths are configured to carry signals that include both header information and data.

13. The PLD of claim 5,

wherein the multiplexers are provided in a channel between outputs and inputs of the modules, and

wherein the reconfiguration performed is a partial reconfiguration during operation of the crossbar switch by programming configuration memory array cells to change select inputs of the multiplexers.