Java hardware accelerator using microcode engine
DC CAFCFirst Claim
1. A CPU for executing stack and register-based instructions, comprising:
- execute logic for executing the register-based instructions;
a register file associated with the executed logic; and
a hardware accelerator to process stack-based instructions in cooperation with the execute logic, wherein the hardware accelerator generates a new virtual machine program counter (PC) due to a “
jump subroutine JSR”
or “
jump subroutine wide JSR_W”
bytecode by sign extending the immediate branch offset following the “
jump subrountine JSR”
or “
jump subroutine wide JSR_W”
byte code and adding it to the virtual machine (PC) of the current byte code instruction, computes the return virtual machine program counter and pushes the return virtual machine program counter
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Abstract
A hardware Java™ accelerator is comprised of a decode stage and a microcode stage. Separating into the decode and microcode stage allows the decode stage to implement instruction level parallelism while the microcode stage allows the conversion of a single Java™ bytecode into multiple native instructions. A reissue buffer is provided which stores the converted instructions and reissues them when the system returns from an interrupt. In this manner, the hardware accelerator need not be flushed upon an interrupt A native PC monitor is also used. While the native PC is within a specific range, the hardware accelerator is enabled to convert the Java™ bytecodes into native instructions. When the native PC is outside the range, the hardware accelerator is disabled and the CPU operates on native instructions obtained from the memory.
151 Citations
22 Claims
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1. A CPU for executing stack and register-based instructions, comprising:
-
execute logic for executing the register-based instructions;
a register file associated with the executed logic; and
a hardware accelerator to process stack-based instructions in cooperation with the execute logic, wherein the hardware accelerator generates a new virtual machine program counter (PC) due to a “
jump subroutine JSR”
or “
jump subroutine wide JSR_W”
bytecode by sign extending the immediate branch offset following the “
jump subrountine JSR”
or “
jump subroutine wide JSR_W”
byte code and adding it to the virtual machine (PC) of the current byte code instruction, computes the return virtual machine program counter and pushes the return virtual machine program counter
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2. A central processing unit (CPU) for executing stack and register-based instructions, comprising:
-
execute logic for executing the register-based instructions;
a register file associated with the execute logic; and
a hardware accelerator to process stack-based instructions in cooperation with the execute logic, wherein the hardware accelerator;
maintains an operand stack for the stack-based instructions in the register file such that the operand stack in the register file define a ring buffer in conjunction with an overflow/underflow mechanism for moving operands in the operand stack between the register file and a memory, and loads variables required for processing the stack-based instructions into the register file, generates a new virtual machine program counter due to a “
GOTO”
or “
GOTO_W”
byte code by sign extending the immediate branch offset following the “
GOTO”
or “
GOTO_W”
bytecode and adds it to the virtual machine program counter of the current bytecode instruction,generates a new virtual machine program counter due to a “
JSR”
or “
JSR_W”
bytecode by sign extending the immediate branch offset following the “
JSR”
or “
JSR_W”
bytecode and adding it to the virtual machine PC of the current byte code instruction, computes the return virtual machine program counter and pushes the return virtual machine program counter onto the operand stack,performs a sign extension for the virtual machine SiPush and BiPush byte codes and appends the sign extended data to the immediate field of a register-based instruction being composed based the stack-based instructions;
performs sign extension for virtual machine SiPush and BiPush bytecodes and makes the sign extended data available to be read by the execute logic; and
produces exceptions in respect of selected stack-based instructions. - View Dependent Claims (3, 4)
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5. A central processing unit (CPU) comprising:
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execute logic to receive and process input corresponding to register-based instruction;
a hardware accelerator to process stack-based instructions to produce an output that can be processed by the execute logic;
an operand stack for the stack-based instructions, the operand stack being maintained in a register file as a ring buffer;
an overflow/underflow mechanism for moving operands in the operand stack between a register file and a memory, said register file also storing data associated with the register-based instructions;
a bytecode buffer that receives stack-based instructions from the memory; and
an instruction decode unit coupled to the bytecode buffer to decode instructions received from the bytecode buffer and to provide an indication of how many bytes have been processed; and
a common program counter for the stack-based instructions and the register-based instructions, wherein the common program counter is incremented by the indication of the number of bytes processed. - View Dependent Claims (6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A method for a central processing unit (CPU), comprising:
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for register-based instructions, processing the register-based instructions in execute logic capable of processing the register-based instructions; and
for stack-based instructions, processing the stack-based instructions in a hardware accelerator into input the execute logic is capable of processing, wherein the hardware accelerator generates a new virtual machine program counter (PC) due to a “
jump subroutine JSR”
or “
jump subroutine wide JSR-W”
bytecode by sign extending an immediate branch offset following the “
JSR”
or “
JSR-W”
bytecode and adding it to a virtual machine program counter (PC) of a current bytecode instruction, computes a return virtual machine program counter (PC) and pushes the return virtual machine program counter onto an operand stack. - View Dependent Claims (17, 18, 19, 20, 21, 22)
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Specification