Managing instruction side-effects
First Claim
1. A method, comprising the steps of:
- during execution of an instruction on a computer, in response to an operation of the instruction calling for an architecturally-visible side-effect in an architecturally-visible storage location, storing a value representative of an architecturally-visible representation of the side-effect, a format of the representative value being different than an architecturally-visible representation of the side-effect, and resuming the execution without generating the architecturally-visible side-effect;
later writing the architecturally-visible representation corresponding to the representative value into the architecturally-visible storage location.
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0 Petitions
Accused Products
Abstract
A computer. When an instruction calling for an architecturally-visible side-effect in an architecturally-visible storage location is recognized, a value is stored representative of an architecturally-visible representation of the side-effect, a format of the representative value being different than an architecturally-visible representation of the side-effect. Execution is resumed without generating the architecturally-visible side-effect. Later, the architecturally-visible representation corresponding to the representative value is written into the architecturally-visible storage location. On a context switch, a context of a first process is written and a context of a second process is loaded to place the second process into execution. At least some instructions maintain results in storage resources outside the context resource set, and instructions are marked to indicate whether or not a context switch may be performed at a boundary of the marked instruction. Instruction execution is monitored for a condition that is a superset of a condition whose occurrence is desired to be detected, and a first exception is raised as a result of recognizing the superset condition. Software filters the superset condition to determine whether the monitored condition has occurred, and if so, the software establishes a second exception to be raised after execution of further instructions of the instruction stream. When it is recognized that an instruction is to affect the execution of a second instruction, the processor is set into single-step mode. After the second instruction is executed, the computer is set out of single-step mode.
309 Citations
52 Claims
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1. A method, comprising the steps of:
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during execution of an instruction on a computer, in response to an operation of the instruction calling for an architecturally-visible side-effect in an architecturally-visible storage location, storing a value representative of an architecturally-visible representation of the side-effect, a format of the representative value being different than an architecturally-visible representation of the side-effect, and resuming the execution without generating the architecturally-visible side-effect; later writing the architecturally-visible representation corresponding to the representative value into the architecturally-visible storage location. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A computer, comprising:
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circuitry designed to recognize an operation of an instruction calling for an architecturally-visible side-effect in an architecturally-visible storage location, and in response, to store a value representative of an architecturally-visible representation of the side-effect, a format of the representative value being different than an architecturally-visible representation of the side-effect, and to resume the execution without generating the architecturally-visible side-effect; circuitry and/or software designed to later write the architecturally-visible representation corresponding to the representative value into the architecturally-visible storage location. - View Dependent Claims (10, 11, 12)
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13. A method, comprising the steps of:
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storing a context of a first process and loading a context of a second process to place the second process into execution, each context comprising a set of resources to be reloaded whenever a process associated with the context is reloaded for execution; at least some instructions executed in a multi-stage execution pipeline of the computer maintaining results in storage resources outside the context resource set, instructions for execution by the pipeline being marked to indicate whether or not a context switch may be performed at a boundary of the marked instruction. - View Dependent Claims (14, 15)
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16. A computer, comprising:
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context switch software programmed to store a context of a first process and to load a context of a second process to place the second process into execution, each context comprising a set of resources to be reloaded whenever a process associated with the context is reloaded for execution; a multi-stage execution pipeline of a computer, at least some instructions executed in the pipeline maintaining results in storage resources outside the context resource set, instructions for execution by the pipeline being marked to indicate whether or not a context switch may be performed at a boundary of the marked instruction. - View Dependent Claims (17, 18, 19, 20, 21)
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22. A method, comprising the steps of:
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during hardware execution of an instruction stream, recognizing a condition that is a superset of a condition whose occurrence is desired to be detected, and raising a first exception as a result of recognizing the superset condition; in software, filtering the superset condition to determine whether the desired condition has occurred, and if so, gathering further information about the condition; if the desired condition is determined to have occurred, establishing a second exception to be raised after execution of further instructions of the instruction stream, and making the further information available for a handler of the second exception. - View Dependent Claims (23)
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24. A computer, comprising:
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an instruction execution pipeline designed to execute instructions, and to monitor the executing instructions for a condition arising during execution that is a superset of a condition whose occurrence is desired to be detected, and to raise a first exception as a result of recognizing the superset condition; software designed to filter the superset condition to determine whether the monitored condition has occurred, and if the monitored condition is determined to have occurred, to gather further information about the condition, and to establish a second exception to be raised after execution of further instructions of the instruction stream, and to make the further information available for a handler of the second exception. - View Dependent Claims (25, 26, 27, 28, 29, 30, 31, 32, 33)
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34. A method, comprising the steps of:
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during execution of a program on a computer, recognizing in hardware a condition in which an instruction is to affect the function to be performed by a second instruction, and in response, setting the processor into single-step mode; taking a single-step exception after executing the second instruction, and setting the processor out of single-step mode. - View Dependent Claims (35)
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36. A computer, comprising:
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hardware designed to recognize a condition rising during execution of an instruction on a computer, in which the instruction is to affect the function to be performed by a second instruction; hardware and/or software designed to respond to the recognizing by setting a processor of the computer into single-step mode; and hardware and software designed to respond to execution of the second instruction by setting the computer out of single-step mode. - View Dependent Claims (37, 38, 39, 42, 43, 44, 45)
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40. A computer, comprising:
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hardware designed to recognize a condition rising during execution of an instruction on a computer, in which the instruction is to affect the execution of a second instruction, wherein the first instruction and second instructions are generated by an instruction decoder in response to a single instruction fetched from a memory; hardware and/or software designed to respond to the recognizing by setting a processor of the computer into single-step mode; and hardware and software designed to respond to execution of the second instruction by setting the computer out of single-step mode. - View Dependent Claims (41)
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46. A method, comprising the steps of:
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during execution of a program on a computer, recognizing in hardware a juxtaposition in memory of first and second instructions is to affect the function to be performed by the two instructions, and in response, setting the processor into single-step mode; taking a single-step exception after executing the second instruction, and setting the processor out of single-step mode. - View Dependent Claims (47, 48, 49)
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50. A computer, comprising:
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hardware designed to recognize a condition rising during execution of instructions on a computer, the condition being a juxtaposition in memory of first and second instructions is to affect the function to be performed by the two instructions; hardware and/or software designed to respond to the recognizing by setting a processor of the computer into single-step mode; and hardware and software designed to respond to execution of the second instruction by setting the computer out of single-step mode. - View Dependent Claims (51, 52)
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Specification