Phototransistor of CMOS image sensor and method for fabricating the same

• US 7,229,878 B2
• Filed: 07/05/2005
• Issued: 06/12/2007
• Est. Priority Date: 07/05/2004
• Status: Expired due to Fees

• Current Assignee: Dongbuanam Semiconductor, Inc. (DB HiTek Co., Ltd.)
• Original Assignee: DONGBU ELECTRONICS CO., LTD. (DB HiTek Co., Ltd.)
• Inventors: Jeon, In Gyun
• Primary Examiner(s): Estrada, Michelle
• Assistant Examiner(s): Stark, Jarrett J.
• Application Number:
  US11/175,524
• Publication Number:
  US 20060001121A1
• Time in Patent Office: 707 Days
• Field of Search: 438/128, 438/586, 438/597, 438/598, 438/246, 256/E21.551, 256/E21.585
• US Class Current: 438/246
• CPC Class Codes: H01L 27/14603 Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14689 MOS based technologies

Abstract

A phototransistor of a CMOS image sensor suitable for decreasing the size of layout, and a method for fabricating the phototransistor are disclosed, in which the phototransistor includes a first conductive type semiconductor substrate; an STI layer on the first conductive type semiconductor substrate, to define an active area and a device isolation area in the first conductive type semiconductor substrate; a second conductive type well in the first conductive type semiconductor substrate; a gate line on the first conductive type semiconductor substrate; an ohmic contact layer in the second conductive type well, wherein the ohmic contact layer is overlapped with the gate line in state of interposing the STI layer therebetween; and a contact to connect the gate line with the ohmic contact layer through the STI layer.

Claims

1. A method for fabricating a phototransistor of a CMOS image sensor comprising:

defining an active area and a device isolation area in a first conductive type semiconductor substrate by forming an STI layer in the first conductive type semiconductor substrate;

forming a second conductive type well in the first conductive type semiconductor substrate, wherein the first conductive type is different from the second conductive type;

forming a gate oxide layer on art entire surface of the first conductive type semiconductor substrate;

forming a contact hole for exposing the predetermined portion of the second conductive type well below the STI layer by selectively removing the gate oxide layer and the STI layer;

forming an ohmic contact layer by implanting second conductive type impurity ions into the second conductive type well below the contact hole using the gate oxide layer as a mask;

forming a contact by filling the contact hole with a conductive material; and

forming a gate line over the first conductive type semiconductor substrate including the contact.

2. The method of claim 1, further comprising forming source and drain at opposite sides of the gate line in the second conductive type well by implanting highly doped first conductive type impurity ions to the first conductive type semiconductor substrate using the gate line as a mask.

3. The method of claim 1, wherein a polysilicon is formed over the entire surface of the first conductive type semiconductor substrate including the contact hole, and is then patterned to remain on predetermined portions for the contact and the gate line, so as to form the contact and the gate line at the same time.

4. The method of claim 1, wherein implanting second conductive type impurity ions comprises implanting impurity ions at a high concentration.

5. The method of claim 1, wherein the gate line is formed ohmic contact layer.

6. The method of claim 1, wherein the ohmic contact layer directly contacts wit the contact.

7. The method of claim 1, wherein the ohmic contact layer electrically connects with the gate line.

8. The method of claim 1, wherein the second conductive type well has a uniform depth.

9. The method of claim 1, wherein forming a second conductive type well comprises implanting impurity ions.

10. The method of claim 9, wherein forming a second conductive type well comprises diffusing the implanted impurity ions.

11. The method of claim 1, wherein forming a second conductive type well comprises implanting N-type impurity ions.

12. The method of claim 1, wherein implanting second conductive type impurity ions comprises implanting N-type impurity ions.

13. The method of claim 1, wherein the gate oxide layer remains over a top surface of the STI layer following forming the contact hole.

14. The method of claim 1, wherein a portion of the ohmic contact layer is formed below the STI layer.

15. The method of claim 14, wherein the ohmic contact layer overlaps with the gate line.

16. The method of claim 14, wherein the gate line is formed on the gate oxide layer.