Clock diagnostics

• US 7,230,884 B2
• Filed: 01/05/2004
• Issued: 06/12/2007
• Est. Priority Date: 01/03/2003
• Status: Active Grant

• Current Assignee: Sapling Company, Incorporated
• Original Assignee: Sapling Company, Incorporated
• Inventors: Shemesh, Ilan
• Primary Examiner(s): YAN, REN LUO
• Application Number:
  US10/751,575
• Publication Number:
  US 20040167739A1
• Time in Patent Office: 1,254 Days
• Field of Search: 368/46, 368/47, 368/59, 368/60, 340/539.24, 702/193, 714/26, 714/712, 714/713
• US Class Current: 368/46
• CPC Class Codes: G04C 13/022 via existing power distribution lines

Abstract

Disclosed is a clock for use in a master/slave clock system, including a system and method for semi-automatically performing diagnostic self-tests on the status and operability of a plurality of components of one or more secondary clocks. The invention addresses a multitude of diagnostic and problem detection issues, including “no fault found.”

Claims

1. A clock comprising:

a slave clock including a microprocessor and adapted to be coupled to a master clock;

the microprocessor coupled to a memory, a manually-operable control device, a time display and a diagnostic indicator display;

the microprocessor further configured to receive commands from the master clock;

data and diagnostic software instructions stored in the memory,

whereas, upon operation of the control device at the slave clock, or upon receipt of a command from the master clock, the instructions cause the microprocessor to enter a diagnostics mode, to execute semi-automatic diagnostic self-tests on current status and operability or inoperability of components and functions of the slave clock, to display results of the self-tests via the diagnostic indicator display, and to return the slave clock to a normal clock mode following completion of the self-tests;

the diagnostic self-tests including at least three of the following;

determination of communication protocol type used by the slave clock, determination of an ability or inability of the slave clock to receive data from the master clock, determination of motor and drive gear operability or inoperability, determination of current software version in use by the slave clock, determination of presence or absence of electrical power from a power supply, determination of whether a signal is being received from an optical switch at the slave clock, determination of whether data can be properly read into and out of the memory at the slave clock, and determination of how much time has passed since the slave clock received a communication from the master clock.

2. A master/slave clock system comprising:

a master clock;

at least one slave clock including a microprocessor and coupled to the master clock;

the microprocessor coupled to a memory, a manually-operable control device, a time display and a diagnostic indicator display; and

data and diagnostic software instructions stored in the memory;

whereas, upon operation of the control device at the slave clock or upon receipt by the slave clock of a command from the master clock, the instructions in the memory cause the microprocessor to enter a diagnostics mode, to execute semi-automatic diagnostic self-tests on current status and operability or inoperability of components and functions of the slave clock, to display results of the tests via the diagnostic indicator display, and to return the slave clock to a normal clock mode following completion of said self-tests;

said diagnostic self-tests including at least three of the following;

determination of communication protocol type used by the slave clock, determination of an ability or inability of the slave clock to receive data from the master clock, determination of motor and drive gear operability or inoperability, determination of current software version in use by the slave clock, determination of presence or absence of electrical power from a power supply, determination of whether a signal is being received from an optical switch at the slave clock, determination of whether data can be properly read into and out of the memory at the slave clock, and determination of how much time has passed since the slave clock received a communication from the master clock.