Method and apparatus for accessing management information base data
First Claim
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1. A method in a network element comprising:
- collecting a first set of management information base (MIB) data by a first processing circuit in a framer into a framer'"'"'s memory, the first processing circuit to perform framing operations;
maintaining by a second processing circuit a second set of MIB data that is periodically updated with the first set of MIB data by the second processing circuit, wherein the second set of MIB data is maintained separately from the first set of MIB data, and the second processing circuit is separate from the first processing circuit; and
in response to a request for the MIB data, transmitting the second set of MIB data by the second processing circuit, andwherein the first set of MIB data is maintained by the first processing circuit of the framer while the second set of MIB data is maintained by the second processing circuit, the second processing circuit being a field programmable gate array.
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Abstract
A method and apparatus for accessing management information base data is described. A method in a network element comprises collecting a first set of management information base (MIB) data in a framer'"'"'s memory, maintaining a second set of MIB data that is periodically updated with the first set of MIB data, wherein the second set of MIB data is maintained separately from the first set of MIB data; and, in response to a request for the MIB data, transmitting the second set of MIB data.
9 Citations
43 Claims
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1. A method in a network element comprising:
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collecting a first set of management information base (MIB) data by a first processing circuit in a framer into a framer'"'"'s memory, the first processing circuit to perform framing operations; maintaining by a second processing circuit a second set of MIB data that is periodically updated with the first set of MIB data by the second processing circuit, wherein the second set of MIB data is maintained separately from the first set of MIB data, and the second processing circuit is separate from the first processing circuit; and in response to a request for the MIB data, transmitting the second set of MIB data by the second processing circuit, and wherein the first set of MIB data is maintained by the first processing circuit of the framer while the second set of MIB data is maintained by the second processing circuit, the second processing circuit being a field programmable gate array. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A method in a network element comprising:
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in response to a request for management information base (MIB) data, accessing a first set of MIB data that is maintained by a field programmable gate array (FPGA), wherein the MIB data is separate from a second set of MIB data that is used by the FPGA to periodically update the first set of MIB data; collecting the second set of MIB data by a framer into a framer'"'"'s memory, the framer separate from the FPGA, the framer to perform framing operations and maintain the second set of MIB data; and direct memory access writing the first set of MIB data into a memory on a forwarding engine card by the FPGA. - View Dependent Claims (8, 9, 10, 11)
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12. A method in a network element comprising:
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maintaining a first and second set of management information base (MIB) data in separate memory locations, wherein the first set of MIB data is based on received packets processed by a first circuit and the second set of MIB data is maintained by a second circuit based on the first set of MIB data; accessing the second set of MIB data by the second circuit in response to a request for MIB data; creating a set of one or more packets by the second circuit based on the second set of MIB data; and direct memory access writing the set of packets by the second circuit across a bus into memory on a forwarding engine card wherein the first circuit maintains the first set of MIB data and the second circuit maintains the second set of MIB data, wherein the first circuit is a processing circuit of a framer and the second circuit is a field programmable gate array (FPGA) separate from the first circuit, and wherein the second MIB is periodically updated with the first MIB data. - View Dependent Claims (13, 14, 15, 16, 17)
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18. A network element comprising:
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a bus; a forwarding engine (FE) card coupled with the bus, the FE card to forward packets, the FE card including, a packet processing module (PPM) to process packets and having a set of instructions to cause the PPM to post a write request for a management information base (MIB), a bridge coupled with the PPM and the bus, the bridge to transmit requests across the bus and to receive data from the bus, a memory coupled with the PPM, the memory to host the MIB; and an input/output (I/O) card coupled with the bus, the I/O card to receive and transmit packets and including, a framer to collect and maintain MIB data; an ingress field programmable gate array (iFPGA) coupled with and separate from the framer, the iFPGA to collect and maintain a copy of the MIB data, to periodically update its MIB data with the framer'"'"'s MIB data and to service the write request from the PPM. - View Dependent Claims (19, 20, 21, 22)
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23. A machine-readable storage medium that provides instructions, which when executed by a set of one or more processors, cause said set of processors to perform operations comprising:
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posting a write request for a first set of management information base (MIB) data; communicating the write request to a field programmable gate array (FPGA) that maintains the first set of MIB data based on a second set of MIB data maintained by a framer circuit separate from the FPGA; and direct memory access writing the set of MIB data to a memory on a forwarding engine card, wherein the first set of MIB data is periodically updated from the second set of MIB data, and wherein the FPGA collects the first set of data and the framer circuit collects the second set of data. - View Dependent Claims (24, 25, 26)
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27. A machine-readable storage medium that provides instructions, which when executed by a set of one or more processors, cause said set of processors to perform operations comprising:
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collecting a first set of management information base (MIB) data by a first processing circuit in a framer'"'"'s memory, the first processing circuit to perform framing operations; maintaining by a second processing circuit a second set of MIB data that is periodically updated with the first set of MIB data by the second processing circuit, wherein the second set of MIB data is maintained separately from the first set of MIB data, and the second processing circuit is separate from the first processing circuit; in response to a request for the MIB data, transmitting the second set of MIB data by the second processing circuit, wherein the first set of MIB data is maintained by the framer while the second set of MIB data is collected by the second processing circuit, the processing circuit being a field programmable gate array. - View Dependent Claims (28, 29, 30, 31, 32)
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33. A machine-readable storage medium that provides instructions, which when executed by a set of one or more processors, cause said set of processors to perform operations comprising:
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in response to a request for management information base (MIB) data, accessing a first set of MIB data that is collected and maintained by a field programmable gate array (FPGA), wherein the MIB data is separate from a second set of MIB data that is used by the FPGA to periodically update the first set of MIB data; collecting the second set of MIB data by a framer into a framer'"'"'s memory, the framer separate from the FPGA, the framer to perform framing operations and maintain the second set of MIB data; and direct memory access writing the first set of MIB data into a memory on a forwarding engine card by the FPGA. - View Dependent Claims (34, 35, 36, 37)
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38. A machine-readable storage medium that provides instructions, which when executed by a set of one or more processors, cause said set of processors to perform operations comprising:
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maintaining a first and second set of management information base (MIB) data in separate memory locations, wherein the first set of MIB data is based on received packets processed by a first circuit and the second set of MIB data is maintained by a second circuit based on the first set of MIB data; accessing the second set of MIB data by the second circuit in response to a request for MIB data; creating a set of one or more packets by the second circuit based on the second set of MIB data; and direct memory access writing the set of packets by the second circuit across a bus into memory on a forwarding engine card wherein the first circuit collects and maintains the first set of MIB data and the second circuit collects and maintains the second set of MIB data, wherein the first circuit is a processing circuit of a framer and the second circuit is a field programmable gate array (FPGA) separate from the framer, and wherein the second MIB is periodically updated with the first MIB data. - View Dependent Claims (39, 40, 41, 42, 43)
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Specification