Method of fabricating a polysilicon layer

• US 7,235,466 B2
• Filed: 01/31/2005
• Issued: 06/26/2007
• Est. Priority Date: 10/31/2002
• Status: Expired due to Term

• Current Assignee: AU Optronics Corporation
• Original Assignee: AU Optronics Corporation
• Inventors: I-Chang, Tsao
• Primary Examiner(s): Smith; Zandra V.
• Assistant Examiner(s): Au; Bac H.
• Application Number:
  US10/906,007
• Publication Number:
  US 20050106841A1
• Time in Patent Office: 876 Days
• Field of Search: 438/479, 438/482, 438486-488
• US Class Current: 438/487
• CPC Class Codes: H01L 21/02422 Non-crystalline insulating materials, e.g. glass, polymers
• CPC Class Codes: H01L 21/02488 Insulating materials
• CPC Class Codes: H01L 21/02502 consisting of two layers
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02686 Pulsed laser beam

Abstract

A method of fabrication a polysilicon layer is provided. A substrate is provided and then a buffer layer having a plurality of trenches thereon is formed over the substrate. Thereafter, an amorphous silicon layer is formed over the buffer layer. Finally, a laser annealing process is conducted so that the amorphous silicon layer melts and crystallizes into a polysilicon layer starting from the upper reach of the trenches. This invention can be applied to fabricate the polysilicon layer of a low temperature polysilicon thin film transistor liquid crystal display such that the crystals inside the polysilicon layer are uniformly distributed and have a larger average size.

Claims

1. A method of fabricating a polysilicon layer, comprising:

providing a substrate;

forming a first low-k material layer over the substrate;

forming a first set of trenches in the first low-k material layer;

forming an amorphous silicon layer over the first low-k material layer without contacting the substrate; and

conducting a laser annealing process to crystallize the amorphous silicon layer into a polysilicon layer, wherein the polysilicon layer includes a plurality of crystal boundaries and the crystal boundaries are located outside the trenches and between each pair of neighboring trenches.

2. The method of claim 1, wherein the step of forming the amorphous silicon layer comprises filling in the first set of trenches with amorphous silicon.

3. The method of claim 1, further comprising:

forming a second low-k material layer on the first low-k material layer, wherein the second low-k material layer fills in the first set of trenches; and

forming a second set of trenches in the second low-k material layer, wherein the amorphous silicon layer fills in the second set of trenches.

4. The method of claim 3, wherein the step of forming the second set of trenches comprises performing photolithographic and etching processes.

5. The method of claim 3, wherein a material of the second low-k material layer is different from that of the first low-k material layer.

6. The method of claim 1, wherein the step of fanning the first set of trenches comprises performing photolithographic and etching processes.

7. The method of claim 1, wherein the step of conducting the laser annealing process comprises an excimer laser annealing process.

8. The method of claim 1, wherein the first set of trenches is substantially parallel to one another.

9. The method of claim 1, wherein the first low-k material layer is comprised of an organic low-k material.

10. The method of claim 1, wherein the first low-k material layer is comprised of an inorganic low-k material.